cancel
Showing results for 
Search instead for 
Did you mean: 

Knowledge Base Articles

Input Jitter in Synchronous SRAMs

Anonymous
Not applicable

Input Jitter in Synchronous SRAMs

Question: Does Synchronous SRAM like when interfaced with an FPGA sensible to cycle jitter OR does it accept everything as long as timing requirements are met?

 

Answer:      

The device can accept any kind of incoming jitter as long as the input timing parameters specified in the datasheet (especially set up and hold times) are met.

0 Likes
Version history
Revision #:
1 of 1
Last update:
‎Sep 01, 2011 09:05 AM
Updated by:
Anonymous
 
Contributors