Input Jitter in Synchronous SRAMs
Anonymous
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Sep 01, 2011
09:05 AM
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Sep 01, 2011
09:05 AM
Question: Does Synchronous SRAM like when interfaced with an FPGA sensible to cycle jitter OR does it accept everything as long as timing requirements are met?
Answer:
The device can accept any kind of incoming jitter as long as the input timing parameters specified in the datasheet (especially set up and hold times) are met.
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