DMAC is function to be possible to transfer specified amount of data without difficulty by one repeated trigger.
We recommend to use DMAC when there is following function.
And when the use of DMAC is reviewed, at first it is need to confirm whether DMAC for use products has the transfer request factor for use peripheral (UART, A/D, PPG and etc.).
We introduce regarding following item of DMAC.
DMAC has following mode and type.
Combination of Transfer Type and Transfer Mode
Single/Block transfer mode (Block/Step transfer)
This mode is DMA transfer of one time by transfer request of one time.
Transfer size is decided by Block size. In case of large Block size, transfer rate is improved, but actual throughput of CPU is downed.
Continuation transfer mode (demand transfer)
This mode is DMA transfer while transfer request (DREQ) is kept active level.
Assignment of Bus usage to CPU is when transfer times resister becomes to 0 or DREQ input becomes to inactive level.
Burst transfer mode
This mode is DMA transfer of specified transfer times by transfer request of one time.
Assignment of Bus usage to CPU is when transfer times resister becomes to 0.
This type is the mode to read and write by turns.
(This type is transferred after once internal Bus control is latched the data.)
Access is 2 types as following
Internal area (RAM)←→Internal area (I/O),
Internal area (I/O)←→External area (RAM)
This type is the mode to read and write at same time.
(This type is transferred external memory←→external I/O at same time.)
Access type is as following
External area (RAM)←→External area (I/O)
Transfer size of DMAC is 3 kind of type as following.
For transfer trigger of DMAC, there is UART/SIO,A/D,PPG and etc., but it is different for each device. Please refer a list of DMA transfer request in Hardware manuasl.
By setting of transfer times specification resister (DMACT), it is possible to set from 1 time to 65536 times.
DMACT is counted down 1 by transfer of one time.
Specified sizes is transferred with the direction of transfer source address→transfer destination address.
And these addresses are possible to set of decrease, fix and increase.
Each DMA is possible to set whether the interrupt becomes available or not after completing DMA transfer.
DMA transfer completion is occurred when basically specified transfer times is completed.
The interrupt facotr is set by error of transfer request occurrence source (overrun error of UART and etc.). Therefore it is needed to confirm whether the error is occurred or not at occurring the interrupt.