What is the read speed of HyperFlash™ at 100 MHz? How do I calculate it?
Answer: See the HyperFlash datasheet (001-99198 Rev. *H or later) for all reference data used in the following calculations.
There are multiple reading cases that depend on the reading address or reading length. The calculations are for two common types of HyperBus™ reads: 1) random access 4B reads; and 2) continuous sequential reads:
Case 1: 4-byte random access read (e.g., pre-fetch a single instruction)
Latency clock cycles are required according to Table 4 in the datasheet. A 10-clock latency is needed at 100 MHz
As shown in datasheet Figure 31, it takes three clocks to send command-address, latency, and to read data out. This can be explained as follows:
1.5 clocks to send command-address (part of it) + 10 clocks latency at 100 MHz + 0.5 clock + 2 clocks to read data = total 14 clocks to read 2 words
For back-to-back random reads, tCSHI and tCSS should be considered in the calculation. See datasheet Table 53: