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Bit-banding access to individual bits in peripheral registers for FM0+/FM3/FM4 microcontrollers – KBA220576

Bit-banding access to individual bits in peripheral registers for FM0+/FM3/FM4 microcontrollers – KBA220576

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Bit-banding access to individual bits in peripheral registers for FM0+/FM3/FM4 microcontrollers – KBA220576

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Translation - Japanese: FM0+/FM3/FM4 マイクロコントローラ ビットバンディングによるペリフェラル レジスタの各ビットへのアクセス - KBA220576 - Community Translated (JA)


When bit-banding is used to access a bit in peripheral registers, which access size (a byte, a half-word or a word) can be used for the bit-banding access?


The bit-band alias address is word-aligned and can be accessed with any of the access sizes. However, it is recommended to use the minimum access size supported by the targeted register. You can find available access sizes of each peripheral register in “Appendixes – Register Map” sections of Technical Reference Manual for FM0+, FM3 or FM4 microcontroller.

When a read or write instruction to access a bit-band alias address is issued, a read operation (for read instruction) or a read-modifywrite operation (for write instruction) is implicitly executed to the targeted peripheral register with the access size specified in the read/write instruction.

The access size doesn’t matter for most of peripheral registers. However, we need to know some cases that it should be considered.

Please check size of the target register and if there are any other registers in a 32-bit word line containing the target register

If the target is a byte or half-word register, and other registers are located in the same word line, do not access the bit-band alias address with the size larger than the target register. Otherwise, the implicit read/read-modify-write operation may be applied not only to the target register but also to the neighbor registers in the same word line. If the neighbor registers have some hardware controlled bits such as FIFO or status flag, contents of these bits may be lost by the read/read-modify-write operation.

(E.g.) USB Host: Host Error Status (HERR) register and Host Interrupt (HIRQ) register

This is also true for accessing a bit in a register containing the hardware controlled bits. Typical example is Scan Conversion FIFO Data (SCFD) Register. The 32-bit register has a status bit (INVL bit) indicating validity of a scan conversion result in lower half word and a FIFO storing the scan conversion results in upper half word. To know the validity of a scan conversion result, status of the INVL bit might be periodically estimated.

If a bit-band alias address corresponding the INVL bit is accessed with 32-bit word size to read validity of a scan conversion result, the read operation is applied to a whole register width and valid scan conversion data in the FIFO will be shifted out and lost. To avoid this problem, the bit-band alias address should be accessed with byte or half-word size.

(E.g.) DMAC: PB bit and EB, ST bits of Configuration A (DMACA) register

MFS UART Mode: D8 bit and D[7:0] bits of RDR/TDR register in multiprocessor mode

ADC: Lower and higher half-words of Scan Conversion FIFO Data (SCFD) and Priority Conversion FIFO Data (PCFD) Register

Another case to be considered is a write to a bit in write-only register. A bit-band alias write will cause a read-modify-write operation to the register. However, read value of the operation may be undefined. Therefore, an undefined value might be written back to the register excluding the target bit. This may cause unexpected behavior on the peripheral. Do not use bit-band alias access to such registers.

(E.g.) BT: Software-based Simultaneous Startup (BTSSSR) register

For PDL (Peripheral Driver Library) users, please confirm definitions of bit-band alias addresses you are using.

PDL provides macros of bit-band alias addresses for easy access to bits of peripheral registers. The bit-band alias macros are defined with a prefix “bFM_” in peripheral register definitions header file. If the bit-band alias macros you’re using violate the above manners, do not use them.

(E.g.) Lower and higher half-words of Scan Conversion FIFO Data (SCFD) register

Definition in PDL 2.1.0: #define bFM_ADC0_SCFD_INVL *((volatile uint8_t *)(0x424E01B0UL))

→ This is not a problem because the SCFD register is byte-accessed.

Definition in PDL 2.0.2: #define bFM_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL))

→ This may cause a problem and FIFO data will be lost because the SCFD register is word-accessed. Do not use this