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Allowable Skew Between CK and CK# Signals in Cypress HyperFlash Devices – KBA229054

ChaitanyaV_61
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Allowable Skew Between CK and CK# Signals in Cypress HyperFlash Devices – KBA229054

Author: SudheeshK_26            Version: **

Translation - Japanese: サイプレス HyperFlashデバイスのCKとCK#信号間の許容スキュー - KBA229054 - Community Translated (JA)

Cypress 1.8V I/O HyperFlash™ devices need differential clock inputs (CK and CK#) to perform read and write operations. Ideally, the clock periods of both CK and CK# signals should be equal and should not change from one clock cycle to the next one so that the voltage on CK and CK# signals become VCCQ/2 every half clock cycle. However, because of noise, there can be skew between CK and CK# signals. Cypress HyperFlash devices can function properly even if there is a skew between CK and CK# signals. The following formula can be used to calculate the maximum allowable skew:

Maximum allowable skew = 2 x (VIXmax – VDDQ/2) / (Minimum input slew rate of CK/CK# signals)

VIX: AC Differential Crossing Voltage

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Example: Consider the device S26KS512S (page 86 of the datasheet)

VCCQ = 1.8 V

VIXmax = VCCQ x 0.6 = 1.08 V

Minimum input slew rate for CK and CK# signals (note 126) = 1 V/ns (minimum)

Maximum allowable skew between CK and CK# signals = 2 x (1.08 V – 0.9 V) / (1 V/ns) = 2 x 0.18 ns= 360 ps

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