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HI,
I use the S27KS0641's model emulate the controller,but Modelsim hint "Error: C:/Users/Bruce/Desktop/Psram_Interface/s27ks0641.v(375): $skew( negedge CSNeg:41697163 ps, posedge CSNeg:42007173 ps, 1 ps );".The ck is 100MHz,and only Write 32 bytes,we have provided 12 cycles of latency. There is only 310ns from the negedge of CS to the posedge of CS.What the error tell us?Thank you.
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These pictures are from the file of S27KS0641's model.tskew_CSNeg_CSNeg is set 1,it's 1ps,1ns or 1us?
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Hello,
Please make sure you are using the latest Verilog model available in our website for simulation.
Latest model is available at: https://www.cypress.com/documentation/models/verilog/s27kl0641-s27ks0641-verilog .
Are you using SDF file for simulation? If not, please use SDF file and see if you are still facing this issue.
Thanks and Regards,
Sudheesh