Microcontrollers Forum Discussions

Hello,

I am trying to flash littlefs filesystem on the qspi external serial flash memory in XMC7100 V1.1. As I see library mtb-littlefs is not included in the XMC7100 kit but i have included the mtb-littlefs from PSoc6 Kit to my project and in makefile included target as XMC7100 (my board).

BOARD: XMC7100 EVK Lite v1.1

Memory: External QSPI flash memory

These are the errors when I try to builld the file:

Initializing build: mtb-example-psoc6-filesystem-littlefs-freertos Debug APP_KIT_XMC71_EVK_LITE_V1 GCC_ARM

Prebuild operations complete

Auto-discovery in progress...
Auto-discovery complete
Commencing build operations...

Tools Directory: C:/Users/Prasad/ModusToolbox/tools_3.2
"Using linker bsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/COMPONENT_/TOOLCHAIN_GCC_ARM/linker.ld"

Constructing build rules...
Build rules construction complete

==============================================================================
= Building application =
==============================================================================
Generating compilation database file...
-> ./build/compile_commands.json
Compilation database file generation complete
Building 223 file(s)
Compiling ../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c -DCOMPONENT_APP_KIT_XMC71_EVK_LITE_V1 -DCOMPONENT_CAT1 -DCOMPONENT_CAT1C -DCOMPONENT_CAT1C4M -DCOMPONENT_CM7 -DCOMPONENT_CM7_0 -DCOMPONENT_Debug -DCOMPONENT_FREERTOS -DCOMPONENT_GCC_ARM -DCOMPONENT_MW_ABSTRACTION_RTOS -DCOMPONENT_MW_CAT1CM0P -DCOMPONENT_MW_CLIB_SUPPORT -DCOMPONENT_MW_CMSIS -DCOMPONENT_MW_CORE_LIB -DCOMPONENT_MW_CORE_MAKE -DCOMPONENT_MW_FREERTOS -DCOMPONENT_MW_MTB_HAL_CAT1 -DCOMPONENT_MW_MTB_LITTLEFS -DCOMPONENT_MW_MTB_PDL_CAT1 -DCOMPONENT_MW_RECIPE_MAKE_CAT1C -DCOMPONENT_MW_RETARGET_IO -DCOMPONENT_RTOS_AWARE -DCOMPONENT_SOFTFP -DCOMPONENT_XMC7x_CM0P_SLEEP -DCORE_NAME_CM7_0=1 -DCY_APPNAME_mtb_example_psoc6_filesystem_littlefs_freertos -DCY_RETARGET_IO_CONVERT_LF_TO_CRLF -DCY_SUPPORTS_DEVICE_VALIDATION -DCY_TARGET_BOARD=APP_KIT_XMC71_EVK_LITE_V1 -DCY_USING_HAL -DDEBUG -DLFS_THREADSAFE -DTARGET_APP_KIT_XMC71_EVK_LITE_V1 -DXMC7100D_F176K4160  -I. -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1 -Ibsps -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config/GeneratedSource -Ibsps/TARGET_APP_KIT_XMC71_EVK_LITE_V1/config -Ilibs/abstraction-rtos/include -Ilibs/abstraction-rtos -Ilibs/abstraction-rtos/include/COMPONENT_FREERTOS -Ilibs/cat1cm0p/COMPONENT_CAT1C -Ilibs/cat1cm0p -Ilibs/clib-support -Ilibs/clib-support/TOOLCHAIN_GCC_ARM -Ilibs/cmsis/Core/Include -Ilibs/cmsis/Core -Ilibs/cmsis -Ilibs/core-lib/include -Ilibs/core-lib -Ilibs/freertos/Source/include -Ilibs/freertos/Source -Ilibs/freertos -Ilibs/freertos/Source/portable/COMPONENT_CM7 -Ilibs/freertos/Source/portable -Ilibs/freertos/Source/portable/COMPONENT_CM7/TOOLCHAIN_GCC_ARM -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/pin_packages -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C -Ilibs/mtb-hal-cat1 -Ilibs/mtb-hal-cat1/COMPONENT_CAT1C/include/triggers -Ilibs/mtb-hal-cat1/include -Ilibs/mtb-hal-cat1/include_pvt -Ilibs/mtb-hal-cat1/source -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C -Ilibs/mtb-pdl-cat1/devices -Ilibs/mtb-pdl-cat1 -Ilibs/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip -Ilibs/mtb-pdl-cat1/drivers/include -Ilibs/mtb-pdl-cat1/drivers -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet/include -Ilibs/mtb-pdl-cat1/drivers/third_party/ethernet -Ilibs/mtb-pdl-cat1/drivers/third_party -Ilibs/retarget-io -I../mtb_shared/mtb-littlefs/latest-v2.X/bd -I../mtb_shared/mtb-littlefs/latest-v2.X -I../mtb_shared/mtb-littlefs/latest-v2.X/include 
../mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.c:487:5: error: 'cy_stc_smif_mem_device_cfg_t' has no member named 'mergeTimeout'
  487 |     .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
      |     ^
make[1]: *** [libs/core-make/make/core/build.mk:283: C:/Users/Prasad/mtw/Littlefs_Filesystem/Littlefs_Filesystem/build/APP_KIT_XMC71_EVK_LITE_V1/Debug/ext/mtb_shared/mtb-littlefs/latest-v2.X/source/lfs_qspi_memslot.o] Error 1
make: *** [libs/core-make/make/core/main.mk:385: secondstage_build] Error 2
"C:/Users/Prasad/ModusToolbox/tools_3.2/modus-shell/bin/make CY_MAKE_IDE=eclipse CY_IDE_TOOLS_DIR=C:/Users/Prasad/ModusToolbox/tools_3.2 CY_IDE_BT_TOOLS_DIR= -j8 --output-sync all" terminated with exit code 2. Build might be incomplete.

When I comment the line:

#if (CY_IP_MXSMIF_VERSION >= 2)
    /** Continuous transfer merge timeout.
     * After this period the memory device is deselected. A later transfer, even from a
     * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
     * This configuration parameter is available for CAT1B devices. */
    //.mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
#endif /* CY_IP_MXSMIF_VERSION */

I get failed to creat spi device block:

Could someone help me with ".mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE" error?

When using the mtb-littlefs through the mtb-shared, how do I enable the cy_hal, freertos and thread in make file?
I tried to add the necessary comments on my application makefile but it is not enabling the corresponding if condition in the files in mtb-shared folder/mtb-littlefs!

best regard,
PrasadA

Hello everyone! Is it possible to directly measure the current running through a DC motor using the BTN9970LV shield? I tried finding the answer in the data sheet and user manual but I was unable to. Thanks for your responses!

This Q&A just discussed P/D Flash, AURIX™ MCU: Error Correction Code (ECC) support - KBA238244

My question: is there special ECC for  RAM and CAN relevant memory, e.g. Message RAM

Hi there,

Can you confirm whether the statement below is true?

"Where a watchdog timeout alarm (CPU or safety) is triggered the microcontroller will always reset"

I am learning about recovery timers and so far through my observation this appears to be true. I find the wording in the manual ambiguous however, where the word "ensure" is used in reference to this.

Thanks

请教大家一个问题

我现在做的boot程序在跳转app程序的时候，如果boot程序和app程序都没有使用中断的情况下可以正常跳转，但是boot程序或app程序有一方面使用中断的话就会进入到debug，boot程序或app程序单独运行时没有问题。下面按照串口中断举例。

调试状态下会卡在下图位置：

我想知道是哪个地方设置的不对或者少设置了什么地方。

Hi,

I am doing a research project using CY8CKIT-042 PSoC4 Pioneer Kit (CY8C4245AXI-483).  The prototype device is powered from a battery of 40mAh capacity. After the normal mode operation when I power OFF the device, the uC enters into deep sleep power saving mode. From the deep sleep mode when I connect charger for charging the battery or press the power ON key then uC exits from deep sleep mode and enters into normal mode.

However in an extreme case, the battery was weak while the time I powered OFF the device then in between the deep sleep operation state the battery was fully drained and there was no power source to the device and uC wad fully turned OFF.

After the above scenario, when I connect a power source to the device the expected behaviour is that the device should turn ON automatically due to the reset signal that appears on connecting the power source. However, in some scenario the device didn't turned ON and a re-flashing of the uC was required for turning ON and resuming the expected behaviour.

Can anyone suggest some root cause for this behaviour and what could the possible solution to avoid it?

Thanks in advance.

IFX_INTERRUPT(OS_CAT2_General_Handler,0,6);
IFX_INTERRUPT(OS_CAT2_General_Handler,0,5);

why i can't install same handler in different priority. It's logically can do as ARM architecture as the processor only use the priority to get the Handler start, i need a solution for installing the same handler (ISR) in different priorities to handle CAT2 interrupts in my project and i can't upload the project as i have a signed NDA.

Hello everyone! I have some questions about tle9879 driver bldc, pwm frequency selection, and would like to get answers.

For the same motor, the motor inductance parameter is measured and the results are measured:

Frequency 1khz ------Ls-900uH Lr-0.8Ω

Frequency 10khz ------Ls-880uH Lr-5.4Ω

Frequency 15khz ------Ls-850uH Lr-10.2Ω

Frequency 20khz ------Ls-830uH Lr-16.1Ω

If you look at it according to impedance, the lower the frequency, the lower the impedance, then the greater the output capability of the motor; conversely, if the frequency is high and the impedance is high, then the output capability will be reduced.

But the actual test to see, the results are not so, ccu6- >T12 is also on the pwm setting frequency 10hkz when the carry capacity is very weak, a little bit of load may be held back; and 20khz than 10khz carry capacity is much stronger. Here may have something to do with the renewal current, but exactly what is not understand.

Anyone who understands the relationship between frequency and torque would be grateful for an answer!

smartconx_target@Q!w2e3r4t5y6u7i8o9p0||/t5/MOTIX-MCU/BLDC-PWM%E9%A2%91%E7%8E%87%E5%92%8C%E6%89%AD%E7%9F%A9%E7%9A%84%E9%80%89%E6%8B%A9/td-p/742036