Code Examples Forum Discussions

Hi,

I've created a project based on some forum discussions regarding generating a polyphonic system.

Here is a project that can generate and mix up to 8 musical notes simultaneously.

It uses only one 8-bit VDAC and op-amp.  It does however use 9 DMA channels with 9 TDs.

Although the project can invoke specific musical notes (A0, C#1, E1, A1, C#2, E2, A2, C#3) by UART command   It can generate many musical notes from C0 (16.35 Hz) to C9 (15804.26 Hz) .  It can also generate frequencies in-between the musical notes if you want.

The project uses a UART @ 115.2Kbps 8N1 to signal which notes to turn ON or OFF.

• '1' - note 1 ON at 110 Hz (A2)
• '!' - note 1 OFF.
• '2' - note 2 ON at 138.591 Hz (C#3)
• '@' - note 2 OFF
• '3' - note 3 ON at 164.814 Hz (E3)
• '#' - note 3 OFF.
• '4' - note 4 ON at 220.0 Hz (A3)
• '$' - note 4 OFF
• ... I hope you can see the pattern here ...
• 'O' - ALL notes OFF.

If all notes are turned on you should get A major chord across 2 2/3 octaves.

There is API calls where you can enter your own note frequencies and will try to scale them as best as possible.

The UART can be replaced with switches if you want.

The code may not be elegant (or bug free).  However it is a proof of concept.

This project is a starting point for your projects.   Enjoy!

Requirements:

• PSoC5LP
• CY8CKIT-059.

This project can be adapted to other kits and PSoCs such as the PSoC3.

Here are some scope plots of the output.

Fig 1 - 220Hz

Fig 2 - 110Hz + 220Hz

Fig 3 - FFT of 110Hz + 220Hz + 440Hz (500Hz span)

Design in PSoC Creator

The design shown in Figure 1 implements continuous updating of the VDAC Component’s output voltage using DMA; the TCPWM block generates the DAC update mode “Strobe edge sync” signals. The DMA transfers are initiated by a trigger signal generated by the previous update’s completion. The VDAC Component is placed into an available CTDAC hardware block and the output voltage waveform is routed to pin P9[6]. An oscilloscope connected to pin P9[6] can display the waveform as Figure 2 below.

Figure 1. PSoC Creator Component Schematic

Figure 2. The test result:

How to design it in Modus Toolbox 2.3:

The same function that develops in MTB has 2 key points that need to solve.

1: The “Strobe edge sync” DAC update mode is NOT configurable in “Device config”.

So, we should re-config it in the “ctdac_cofig” struct like below, pay attention to update Mode

const cy_stc_ctdac_config_t DAC_config_ring =

{

    .refSource = CY_CTDAC_REFSOURCE_VDDA,

    .formatMode = CY_CTDAC_FORMAT_UNSIGNED,

    .updateMode = CY_CTDAC_UPDATE_STROBE_EDGE_SYNC,

    .deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED,

    .outputMode = CY_CTDAC_OUTPUT_VALUE,

    .outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED,

    .deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE,

    .deglitchCycles = 0x22u,

    .value = 0,

    .nextValue = 0,

    .enableInterrupt = true,

    .configClock = false,

    .dividerType = CY_SYSCLK_DIV_8_BIT,

    .dividerNum = 0,

    .dividerIntValue = 0,

    .dividerFracValue = 0,

};

2: TCPWM overflow connect to DAC strobe:

Now the Modus Toolbox 2.3 doesn’t support the UDB DSI config, essentially, all functions are registers configuration, so we need to copy the corresponding file from IDE PSoC Creator to Modus Toolbox.

Steps to transplant this function, copy the file “cydevice_trm.h” and copy the UDB DSI config part from the “cyfitter_cfg.c” to the Modus Toolbox project.

See my project's new API which names “custom_UDB_DSI_Config()”.

For the “DAC, TCPWM, DMA” driver code, see the attached project.

Here is an example of the ADC_SAR operating in stroboscope mode. Using this mode of operation it is possible to acquire a waveform with resolution ~50ns, which is about 20x times faster than ADC_SAR can provide in continuous sampling mode.

       The drawback of that technique is that the incoming signal has to be periodic and stable over the time of acquisition. With conditions fulfilled, a single ADC snapshot is made per each period, and offset delay is slowly incremented for each next snapshot. The PSoC5 SAR_ADC sampling time is 4 clocks, which can be as high as 18 MHz, which should define the resolution of this approach. Surprisingly, the observed resolution is higher (~1 clock), which needs further research. I suspect that in 8-bit mode the majority of the charge is collected during the first ADC sampling clock.

      The project uses KIT-059 onboard 22pf capacitor (C41) as device under test. A short PWM pulse (~500ns) is charging this capacitor, producing short ramp waveform. PWM_1 period is set to 32 clocks. PWM_2_tc serves as a strobe signal, and its period is set to 33 clocks. The ADC is preset into the ready state by API, waiting for a hardware trigger, which is fired every 32 periods of PWM_1. A simplified diagram is shown below.

Project shows that using SAR_ADC (PSoC5) it is possible to resolve signals with time step of about 50ns, which should be sufficient for sampling <10MHz signal. To drive the ADC the input signal should be of low-impedance and sufficient amplitude (~1V), so some wide-band  (>20MHz) external Opamp may be needed as ADC front end.

The project uses community libraries:

SerialPlot: interface to real-time data charts

PSoC Annotation Library v1.0 (optional)

/odissey1

Figure 1. ADC is in externally strobed mode. DMA is gated by software and hardware. The gate is hardware triggered. DMA transfers ADC data into RAM buffer for later processing and visualization.

Figure 2. Pulse train generator. PWM_1 produces 8 clocks wide pulse, with period 32 clocks. PWM_2 generates a strobe pulse, with period of 33 clocks. Device under test is KIT-059 onboard capacitor (22pF), producing short ramp test signal. Note that o-scope probe capacitance (~20pf) also affects signal shape and amplitude.

Figure 3. Acquired data is visualized using SerialPlot charting tool and corresponding interface component. Communication with computer is performed through UART.

Figure 4. Project annotation using PSoC Annotation Library. Note that the o-scope probe capacitance affects signal shape. The signal amplitude almost doubles with probe disconnected. A low capacitance (~1.5pF) active probe is recommended.

Figure 5. Yellow trace - ramp signal from DUT, Cyan - PWM_1 sync (tc) signal, Fuchsia - ADC strobe, Blue - DMA trigger. Ramp's risetime is approx. 500ns.

Figure 6. Acquired waveform visualized using SerialPlot charting software. Two full periods of 32 points each, acquired with interval 1sec, are displayed. Estimated ADC resolution is approx. 50 ns.

少し前にフレキのセンサー電極を使用したサンプルを上げてみました。

A little ago, I posted a sample using the flex PCB of Elephantech.

https://community.cypress.com/t5/Code-Examples/A-CapSense-sample-using-an-Elephantech-flex-PCB-electrode/td-p/281465

今回は、同エレファンテック社製の PEDOT というタイプの電極部が透明なセンサー電極を使わせていただけたので、あまり例がなかったのではないかと思う、透明電極を使用した CapSense のデモを作成してみました。

This time, I got a chance to use their PEDOT sensor electrode, which has transparent electrode(s)!

So I hacked up a little sample using this sensor electrode.

例によって CY8CKIT-044 に SPI 経由で ILI9341 搭載の 320x240 の TFT を接続して、TFT の上に透明な両面テープを使用してセンサー電極を固定しました。

As usual, I used CY8CKIT-044 and an ILI9341/SPI type 320x240 TFT, I found a cheaper one to play with 😉

I used a double sided clear tape to fix the sensor on top of the TFT.

プログラムを起動するとトップ画面が表示されます。

透明な CapSense ボタンの下の絵が透けて見えるので、

ボタン毎に色や文字を設定できます。

When started the program shows the "top" screen.

Since the button is transparent, we can see the graphics (color and text) under the buttons.

ここで [ measure ] ボタンをタッチしますと、テストライブラリを使用して

各電極の容量を測定して表示します。

If we touch [ measure ] button here, PSoC measures the capacitance(s) of each electrode

and shows it in the screen below.

ここで [ menu ] ボタンをタッチすると、当然ながら

メニュー画面が表示されます。

Needless to say, if we touch [ menu ] button here,  menu screen will be shown.

ここで [ help ] ボタンをタッチすると、あっさり系のヘルプ画面が表示されます。

ここでのボタン選択肢は [ top ] だけになり、使わないボタンは黒くなっていることにご注意ください。

If we touch [ help ] button,  the quite simple help screen will be shown.

Note that the buttons of both side are disabled and shown in black.

また、メニュー画面で、[ test ] をタッチすると

緑色の箱を動かすテスト画面になります。

On the other hand, if we touched [ test ] button in the menu screen,

the program enters the "Move Box Test" mode.

ここで [ << ] ボタンをタッチすると緑色の箱が左に移動します。

Touching [ << ] button moves the green rectangle to the left.

一番左まで移動すると [ << ] ボタンが無効になって

ボタンが黒くなり、反応しなくなります。

When the green rectangle reaches the left side,

the left [ << ] button is disabled and shown in black.

同様に一番右まで移動すると [ >> ] ボタンが無効になって

ボタンが黒くなり、反応しなくなります。

Similarly at the right most side, the right [ >> ] button is disabled

and shown in black.

schematic / 回路図

Pins / ピン

Additional parts used / 追加使用した部品

TFT display / TFT ディスプレイ

https://www.amazon.co.jp/dp/B072N551V3/

Flex adapter board / フレキからの変換基板

https://www.aitendo.com/product/19419

bread board / ブレッドボード

これは TFT 基板と CY8CKIT-044 の配線及び TFT 基板を安定させるために

2つ使用しました。

I used a couple of these, to connect the TFT board and CY8CKIT-044,

as well as to stabilize the TFT board.

https://akizukidenshi.com/catalog/g/gP-05155/

double sided clear tape / 透明な両面テープ　ニトムズ  T284

https://www.amazon.co.jp/%E3%83%8B%E3%83%88%E3%83%A0%E3%82%BA-%E8%B6%85%E9%80%8F%E6%98%8E%E4%B8%A1%E9%9D%A2%E6%8E%A5%E7%9D%80%E3%82%B7%E3%83%BC%E3%83%88-100mm%C3%97100mm-2%E6%9E%9A%E5%85%A5%E3%82%8A/dp/B01M4GBPNU

通常、CapSense のボタンといえば印刷されている静的な感じのものが多いと思いますが、

動的にボタンの表示を変えたり、ボタンを無効にすることが出来るというのは作っていて面白かったです。

同時に、自分の美的センスの無さも再確認してしまいましたが・・・ orz

Usually, a CapSense button has a static appearance, it was fun programing dynamically changing and enabled/disabled buttons.

Meantime, I missed my sense of colors ... orz

moto

(Edited) Title changed from "using and" to "using an"... typo

Hi,

This is a demo project showing 8-bit Sine (or arbitrary shape) wave generation using custom component (WaveGen) and standard PWM. The wave generator is RAM-DMA-PWM bridge transferring 8-bit data from RAM buffer to PWM. The PWM period is set to 255 to match 8-bit incoming data. Sine wave frequency is controlled with high resolution by the DDS32 generator.

The demo project provides examples of 32 and 256 wave points/period. External RC-filtering of the PWM output needed to produce a smooth sine wave. Like with all PWM-generated analog signals, the maximum achievable output frequency is quite limited. The upper frequency for this design is limited by the maximum DDS output frequency (BUS_CLK/2). For example, using 32 samples/period, Fmax = (BUS_CLK/2) / ( 256 x 32) = 2.9 kHz.

Draft version of the WaveGen component is included in the project. The DDS32 component can be found here:

Re: DDS24: 24-bit DDS arbitrary frequency generator component

/odissey1

Figure 1. Sine wave production using RAM-DMA-PWM bridge (WaveGen) and DDS32.

Figure 2. Yellow trace - PWM output at 32 points/period, Cyan trace - WaveGen reference signal.

Hi,

This sample program is run on CY8CKIT-149 (PSoC 4100S Plus). This is a sample that dynamically modifies the duty cycle of TCPWM. According to Arch TRM, it's recommended that you don't modify the compare register directly, swap it for the value via compare buffer register. The actual timing of swapping is when TC event occurs while swap is enabled. In this sample, TC event is generated by software trigger. The compare value of TCPWM for LED output changes at 1 second intervals.

Please refer to

- PSoC4100S/4100S Plus Arch TRM (Doc No. 002-10621) : 18.3.4.2 How It Works

- PSoC4 TCPWM Component Datasheet (Doc No. 002-10078)

    PWM_Start();

    PWM_WritePeriod(65535u);

    PWM_WriteCompare(10000u);

    PWM_WriteCompareBuf(60000u);

    PWM_SetCompareSwap(1u);   

    for(;;)

    {

        CyDelay(1000);

        PWM_TriggerCommand(PWM_MASK, PWM_CMD_CAPTURE);

    }