MA12070P MSEL Register Reading

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Haldi
Level 1
Level 1
5 sign-ins First reply posted First question asked

Hello,

I purchased this Raspberry compatible board from eBay and tried to make it work using SqueezElite-ESP32 software on a WaveShare ESP32 single board using the ESP32 one board.

There are still a few glitches with the correct startup procedure...

 

But here's my problem:

How do you read the MSEL register?

Haldi_0-1699485762839.png

I got output 0x05, which would be 101.

What does MSEL [2:0] mean? Bit 2 and bit 0?

Does this mean that MSEL0 and MSEL1 are both high in my 101 case? This should not be the case. Because I only need BTL modes with MSEL0 high and MSEL1 low.

 

Second question:

Registry 124 issued error 0x04, which appears to be a bit 2 pll error.

Haldi_1-1699486010882.png

Clock System
The MA12070P integrates a clock system consisting of an input clock crossover, PLL, low jitter low TC oscillator
(2.8224 MHz) and control logic. At the CLK input pin, the MA12070P requires a digital serial audio sample to be connected to the CLK input.
The MA12070P requires a digital serial audio sample to be input. This CLK input signal provides a reference to the internal PLL via the input
This CLK input signal provides a reference to the internal PLL through the input clock frequency divider circuit. The CLK frequency is automatically detected by the MA12070P, and when a valid frequency is detected, the corresponding input crossover ratio is selected.
When a valid frequency is detected, the corresponding input division ratio is selected to generate the correct reference clock for the PLL internally. PLL Splitter
ratio is also selected as a function of the CLK base frequency (2.8224 or 3.072 MHz).
The clock of the internal DAC is derived from the PLL, or at some CLK rate, which is a split version of the CLK input.
Table 8-11 lists the valid audio sample rate (fs) and CLK frequency combinations, as well as the maximum number of supported VLP channels.
Table 8-11 lists the valid audio sample rate (fs) and CLK frequency combinations, as well as the maximum number of VL P channels supported.

 

What can be done about the PLL error? It's internal, depending on the input signal to the ESP32, right?

 

 

Greetings.

 

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Pranava_YN
Moderator
Moderator
Moderator
100 likes received 500 replies posted 250 solutions authored

Hi,

Sorry for delay in responding.

In the msel_mon register, please consider only the last 2 bits of the register. In your case, it is 01 which corresponds to MSEL pins. You can ignore the third bit.

Best regards,
Pranava

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Haldi
Level 1
Level 1
5 sign-ins First reply posted First question asked

I got the Schematics,

Haldi_0-1699616935176.png

 

MSEL1 is always connected to Ground.

Still don't know how what 101 means.

 

But the PLL Error was probably only because the chip got connected to i2c before the connection was fully stable.

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Pranava_YN
Moderator
Moderator
Moderator
100 likes received 500 replies posted 250 solutions authored

Hi,

Sorry for delay in responding.

In the msel_mon register, please consider only the last 2 bits of the register. In your case, it is 01 which corresponds to MSEL pins. You can ignore the third bit.

Best regards,
Pranava
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