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ZihengYuan
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Hello, I have constructed an H-bridge inverter for AC power cycling. The first leg uses IGBTs, while the second leg uses SiC MOSFETs. All driver ICs utilized are 1ED3122. During the debugging process, the upper switch of the second bridge arm frequently experiences driver chip breakdown (all pins of the secondary side are shorted), despite the voltage level being only 200V-300V, and the devices remain undamaged. So what could be the cause of this issue?
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yifei_y
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Not exactly. Following is the equivalent circuit of an IGBT:

yifei_y_0-1712640516342.png

The gate current flows through RLC path consisted with Rgate, input capacitance and parasitic inductance. At the moment of turn-on gate current flows with high dig/dt and generates VGS spike. This spike is applied only at parasitic inductance and does not affect internal die.

 

在原帖中查看解决方案

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yifei_y
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Hi ZihengYuan, it is hard to find the reason according to the description, do you have any schematic and waveforms for us to review?

Regards,

YF

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ZihengYuan
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The problem has been solved, but  I have observed gate voltage drop in both the upper device of IGBT leg

Tek002.png

Tek001.png

Tek007.png

   

(IHW30N120R5XKSA1) at turn-on. The following is the adopted driving scheme and the test results. So how can I solve this problem?Thanks!

The blue line is the voltage of the inductive load, the yellow line is the Vgs of the lower IGBT device, the red line is the inductive current, and the green line Vgs of the upper IGBT device

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ZihengYuan
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Here is the driver scheme

image.png

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yifei_y
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This is normal. The VGE spike during on process is caused by parasitic input capacitance and inductance and does not affect the internal die. The VGE waveform will be smooth if the test point is between parasitics and IGBT die.

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ZihengYuan
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So that means my test point is too close to the IGBT die?  If this is the reason, the SiC MOSFET will also have this spike, but I can not see this spike when I change the IGBT to SiCMOSFET.

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yifei_y
Moderator
Moderator
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250 sign-ins 250 replies posted 25 likes received

Not exactly. Following is the equivalent circuit of an IGBT:

yifei_y_0-1712640516342.png

The gate current flows through RLC path consisted with Rgate, input capacitance and parasitic inductance. At the moment of turn-on gate current flows with high dig/dt and generates VGS spike. This spike is applied only at parasitic inductance and does not affect internal die.

 

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ZihengYuan
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Ok, but why don't I see this voltage spike on SiC MOSFETs, or is this more common on IGBTs?

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