Static Timing Analysis

Project : Vj_GSM
Build Time : 02/26/15 22:47:28
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
UART_1_IntClock CyHFCLK 76.677 kHz 76.677 kHz 44.041 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.041 MHz 22.706 13018.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 4.359
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.227
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.671 MHz 22.386 13019.281
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 4.039
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.227
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.219 MHz 21.636 13020.031
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.289
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.227
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.494 MHz 21.508 13020.159
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 3.161
macrocell2 U(0,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.227
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 50.464 MHz 19.816 13021.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 5.680
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.247
macrocell4 U(1,0) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.249
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 68.013 MHz 14.703 13026.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 2.237
macrocell8 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.266
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 76.840 MHz 13.014 13028.653
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 7.280
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.224
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 78.156 MHz 12.795 13028.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 4.359
macrocell8 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.266
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:TxSts\/status_0 80.160 MHz 12.475 13029.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_status_0\/main_4 4.039
macrocell8 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.266
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 80.483 MHz 12.425 13029.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 4.885
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.514
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 4.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_2 3.160
macrocell6 U(0,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 4.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_2\/main_2 3.161
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 4.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 3.170
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 4.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_0\/main_3 3.172
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:txn\/main_2 4.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:txn\/main_2 3.286
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_2\/main_1 4.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_2\/main_1 3.289
macrocell7 U(0,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_1\/main_1 4.693
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_1\/main_1 3.443
macrocell6 U(0,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_0\/main_1 4.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_0\/main_1 3.444
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 4.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 3.454
datapathcell1 U(1,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_41/main_0 2.514
macrocell1 U(1,0) 1 Net_41 Net_41/main_0 Net_41/q 3.350
Route 1 Net_41 Net_41/q Tx_1(0)/pin_input 6.073
iocell1 P0[1] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.980
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000