Static Timing Analysis

Project : uart
Build Time : 01/05/17 13:20:46
Device : CY8C4247AZI-M485
Temperature : -40C - 85C
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDD_0 : 3.30
VDDD_1 : 3.30
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
UART_SCBCLK CyHFCLK 1.371 MHz 1.371 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 1.371 MHz 1.371 MHz N/A