Static Timing Analysis

Project : Privacy_Central
Build Time : 07/16/15 16:37:06
Device : CYBLE-022001-00
Temperature : -40C - 85C
VDDA : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK CyHFCLK 1.846 MHz 1.846 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 1.846 MHz 1.846 MHz N/A