Static Timing Analysis

Project : Beaudry Encoder Board
Build Time : 02/17/15 16:39:44
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 33.138 MHz
UART_SCBCLK CyHFCLK 115.385 kHz 115.385 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 115.385 kHz 115.385 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 33.138 MHz 30.177 11.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:underflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 4.043
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 34.745 MHz 28.781 12.886
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 2.730
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.237
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 34.786 MHz 28.747 12.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 3.850
Route 1 \QuadDec:Cnt16:CounterUDB:underflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 4.043
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 36.562 MHz 27.351 14.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 4.260
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.237
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 37.179 MHz 26.897 14.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:underflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 4.043
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 37.216 MHz 26.870 14.797
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 2.320
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:underflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 4.043
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.677
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 38.079 MHz 26.261 15.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \QuadDec:Cnt16:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \QuadDec:Cnt16:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \QuadDec:Cnt16:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \QuadDec:Cnt16:CounterUDB:control_7\ \QuadDec:Cnt16:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.314
macrocell1 U(0,1) 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \QuadDec:Cnt16:CounterUDB:count_enable\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:count_enable\ \QuadDec:Cnt16:CounterUDB:count_enable\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 3.217
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 39.214 MHz 25.501 16.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 2.730
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.237
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 39.256 MHz 25.474 16.193
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 2.730
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.960
Route 1 \QuadDec:Cnt16:CounterUDB:overflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_1 2.237
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_1 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 2.677
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 39.267 MHz 25.467 16.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 3.850
Route 1 \QuadDec:Cnt16:CounterUDB:underflow\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \QuadDec:Cnt16:CounterUDB:reload\/main_2 4.043
macrocell5 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/main_2 \QuadDec:Cnt16:CounterUDB:reload\/q 3.350
Route 1 \QuadDec:Cnt16:CounterUDB:reload\ \QuadDec:Cnt16:CounterUDB:reload\/q \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.704
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:quad_A_filt\/q \QuadDec:bQuadDec:error\/main_1 3.474
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,0) 1 \QuadDec:bQuadDec:quad_A_filt\ \QuadDec:bQuadDec:quad_A_filt\/clock_0 \QuadDec:bQuadDec:quad_A_filt\/q 1.250
Route 1 \QuadDec:bQuadDec:quad_A_filt\ \QuadDec:bQuadDec:quad_A_filt\/q \QuadDec:bQuadDec:error\/main_1 2.224
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:Net_1260\/main_1 3.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
Route 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:Net_1260\/main_1 2.245
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ HOLD 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:error\/main_3 3.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/clock_0 \QuadDec:bQuadDec:error\/q 1.250
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ \QuadDec:bQuadDec:error\/q \QuadDec:bQuadDec:error\/main_3 2.245
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Cnt16:CounterUDB:count_stored_i\/main_0 3.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
Route 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Cnt16:CounterUDB:count_stored_i\/main_0 2.307
macrocell2 U(0,1) 1 \QuadDec:Cnt16:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1203\/q \QuadDec:Net_1203\/main_1 3.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/clock_0 \QuadDec:Net_1203\/q 1.250
macrocell10 U(0,1) 1 \QuadDec:Net_1203\ \QuadDec:Net_1203\/q \QuadDec:Net_1203\/main_1 2.307
macrocell10 U(0,1) 1 \QuadDec:Net_1203\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Net_1260\/main_0 4.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Net_1260\/main_0 2.829
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:bQuadDec:error\/main_0 4.079
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:bQuadDec:error\/main_0 2.829
macrocell17 U(1,0) 1 \QuadDec:bQuadDec:error\ HOLD 0.000
Clock Skew 0.000
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.850
statusicell1 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
\QuadDec:bQuadDec:state_1\/q \QuadDec:Net_1251\/main_5 4.350
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,1) 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/clock_0 \QuadDec:bQuadDec:state_1\/q 1.250
Route 1 \QuadDec:bQuadDec:state_1\ \QuadDec:bQuadDec:state_1\/q \QuadDec:Net_1251\/main_5 3.100
macrocell11 U(1,1) 1 \QuadDec:Net_1251\ HOLD 0.000
Clock Skew 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 243.902 MHz 4.100 37.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.850
statusicell1 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/clock_0 \QuadDec:Net_1260\/q 1.250
Route 1 \QuadDec:Net_1260\ \QuadDec:Net_1260\/q \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.850
statusicell1 U(0,0) 1 \QuadDec:Cnt16:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000