Static Timing Analysis

Project : User_SFlash_Write
Build Time : 12/16/15 13:22:48
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 12.000 MHz 12.000 MHz N/A
UART_Console_SCBCLK CyHFCLK 923.077 kHz 923.077 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 12.000 MHz 12.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 12.000 MHz 12.000 MHz N/A
CySYSCLK CySYSCLK 12.000 MHz 12.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_Console_SCBCLK(FFB) UART_Console_SCBCLK(FFB) 923.077 kHz 923.077 kHz N/A