Static Timing Analysis

Project : TimerPWM
Build Time : 08/01/17 10:27:45
Device : CY8C5868LTI-LP038
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz N/A
Clock_1 CyMASTER_CLK 2.000 MHz 2.000 MHz 51.738 MHz
UART_1_IntClock CyMASTER_CLK 307.692 kHz 307.692 kHz 57.022 MHz
CyPLL_OUT CyPLL_OUT 60.000 MHz 60.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 51.738 MHz 19.328 480.672
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_reg\/main_0 2.797
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 52.181 MHz 19.164 480.836
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/clock_0 \Timer_1:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:trig_reg\/main_2 2.593
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_2 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 52.206 MHz 19.155 480.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 1.210
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_reg\/main_1 2.624
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_1 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 60.809 MHz 16.445 483.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 0.760
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb 2.740
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.585
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 5.130
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 4.230
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 62.391 MHz 16.028 483.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_reg\/main_0 2.797
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 62.391 MHz 16.028 483.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 1.210
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_reg\/main_0 2.797
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_0 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.611
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 63.036 MHz 15.864 484.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/clock_0 \Timer_1:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:trig_reg\/main_2 2.593
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_2 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 63.036 MHz 15.864 484.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/clock_0 \Timer_1:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:trig_reg\/main_2 2.593
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_2 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.611
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 63.072 MHz 15.855 484.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 1.210
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_reg\/main_1 2.624
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_1 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.611
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ SETUP 6.060
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 63.072 MHz 15.855 484.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 1.210
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_reg\/main_1 2.624
macrocell7 U(3,4) 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/main_1 \Timer_1:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer_1:TimerUDB:trig_reg\ \Timer_1:TimerUDB:trig_reg\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.611
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 6.060
Clock Skew 0.000
Path Delay Requirement : 3250ns(307.692 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.022 MHz 17.537 3232.463
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 4.518
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.838 MHz 16.437 3233.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.418
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 61.353 MHz 16.299 3233.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 3.479
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.390
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.425 MHz 16.280 3233.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.261
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 64.383 MHz 15.532 3234.468
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.573
macrocell2 U(1,0) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxSts\/status_0 69.066 MHz 14.479 3235.521
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_status_0\/main_1 3.989
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_1 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.390
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 71.911 MHz 13.906 3236.094
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 3.416
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.390
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 72.706 MHz 13.754 3236.246
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 3.264
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.390
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxSts\/status_0 77.531 MHz 12.898 3237.102
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_status_0\/main_2 3.468
macrocell3 U(0,0) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 5.390
statusicell1 U(0,0) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 80.308 MHz 12.452 3237.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_1 5.192
datapathcell1 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u0\ \Timer_1:TimerUDB:sT16:timerdp:u0\/clock \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb 2.140
Route 1 \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 Net_101/main_1 2.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.360
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 Net_101/main_1 2.611
macrocell14 U(3,4) 1 Net_101 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_fall_detected\/main_2 2.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.360
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_fall_detected\/main_2 2.611
macrocell16 U(3,4) 1 \Timer_1:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_rise_detected\/main_2 2.984
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 0.360
Route 1 \Timer_1:TimerUDB:control_4\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer_1:TimerUDB:trig_rise_detected\/main_2 2.624
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_101/main_0 3.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 Net_101/main_0 2.790
macrocell14 U(3,4) 1 Net_101 HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_fall_detected\/main_1 3.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_fall_detected\/main_1 2.790
macrocell16 U(3,4) 1 \Timer_1:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_rise_detected\/main_1 3.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \Timer_1:TimerUDB:control_7\ \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Timer_1:TimerUDB:trig_rise_detected\/main_1 2.797
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:trig_fall_detected\/q \Timer_1:TimerUDB:trig_fall_detected\/main_4 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,4) 1 \Timer_1:TimerUDB:trig_fall_detected\ \Timer_1:TimerUDB:trig_fall_detected\/clock_0 \Timer_1:TimerUDB:trig_fall_detected\/q 1.250
macrocell16 U(3,4) 1 \Timer_1:TimerUDB:trig_fall_detected\ \Timer_1:TimerUDB:trig_fall_detected\/q \Timer_1:TimerUDB:trig_fall_detected\/main_4 2.293
macrocell16 U(3,4) 1 \Timer_1:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:trig_rise_detected\/main_4 3.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/clock_0 \Timer_1:TimerUDB:trig_rise_detected\/q 1.250
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/q \Timer_1:TimerUDB:trig_rise_detected\/main_4 2.593
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:trig_rise_detected\/q Net_101/main_3 3.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/clock_0 \Timer_1:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer_1:TimerUDB:trig_rise_detected\ \Timer_1:TimerUDB:trig_rise_detected\/q Net_101/main_3 2.598
macrocell14 U(3,4) 1 Net_101 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.689
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.701
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.701
macrocell9 U(1,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.468
macrocell10 U(0,0) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 3.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 1.510
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.247
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.573
macrocell11 U(1,0) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.585
macrocell9 U(1,0) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.586
datapathcell1 U(0,0) 1 \UART_1:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 3.589
macrocell12 U(0,0) 1 \UART_1:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.535
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_1
Source Destination Delay (ns)
Pin_1(0)_PAD \Timer_1:TimerUDB:sT16:timerdp:u1\/f0_load 23.749
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_1(0)_PAD Pin_1(0)_PAD Pin_1(0)/pad_in 0.000
iocell3 P0[0] 1 Pin_1(0) Pin_1(0)/pad_in Pin_1(0)/fb 7.922
Route 1 Net_27 Pin_1(0)/fb \Timer_1:TimerUDB:capt_fifo_load\/main_0 6.045
macrocell5 U(3,4) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_0 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT16:timerdp:u1\/f0_load 3.302
datapathcell4 U(2,4) 1 \Timer_1:TimerUDB:sT16:timerdp:u1\ SETUP 3.130
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_101/q Pin_2(0)_PAD 22.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,4) 1 Net_101 Net_101/clock_0 Net_101/q 1.250
Route 1 Net_101 Net_101/q Pin_2(0)/pin_input 6.371
iocell1 P0[5] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.023
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 28.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_263/main_0 2.536
macrocell1 U(0,0) 1 Net_263 Net_263/main_0 Net_263/q 3.350
Route 1 Net_263 Net_263/q Tx_1(0)/pin_input 5.447
iocell2 P12[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.220
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000