Static Timing Analysis

Project : UART4CH
Build Time : 08/23/20 18:30:04
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
Clock_1(routed) Clock_1(routed) 2.000 kHz 2.000 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 57.827 MHz
ADC_SAR_1_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 57.594 MHz
Clock_1 CyMASTER_CLK 2.000 kHz 2.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 57.827 MHz 17.293 24.374
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_postpoll\/main_1 5.617
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_2\/main_8 84.048 MHz 11.898 29.769
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_state_2\/main_8 6.379
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_9 84.161 MHz 11.882 29.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_state_0\/main_9 6.363
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 85.135 MHz 11.746 29.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_last\/main_0 6.227
macrocell24 U(0,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_3 89.710 MHz 11.147 30.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:pollcount_1\/main_3 5.628
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_0\/main_2 89.799 MHz 11.136 30.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:pollcount_0\/main_2 5.617
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_6 89.799 MHz 11.136 30.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_status_3\/main_6 5.617
macrocell23 U(1,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.594 MHz 17.363 1065.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.344
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.603 MHz 17.064 1066.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 4.045
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 61.218 MHz 16.335 1066.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.044
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 61.645 MHz 16.222 1067.111
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,1) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.931
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.000 MHz 16.129 1067.204
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.170
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.496 MHz 16.001 1067.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.982
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 62.909 MHz 15.896 1067.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.605
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 67.114 MHz 14.900 1068.433
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 2.609
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 69.618 MHz 14.364 1068.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.447
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:rx_bitclk_enable\/q \UART:BUART:sRX:RxShifter:u0\/cs_addr_0 71.886 MHz 13.911 1069.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART:BUART:rx_bitclk_enable\ \UART:BUART:rx_bitclk_enable\/clock_0 \UART:BUART:rx_bitclk_enable\/q 1.250
Route 1 \UART:BUART:rx_bitclk_enable\ \UART:BUART:rx_bitclk_enable\/q \UART:BUART:sRX:RxShifter:u0\/cs_addr_0 6.651
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 6.010
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx(0)/fb \UART:BUART:pollcount_0\/main_2 7.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:pollcount_0\/main_2 5.617
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_6 7.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_status_3\/main_6 5.617
macrocell23 U(1,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_3 7.637
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:pollcount_1\/main_3 5.628
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 8.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_last\/main_0 6.227
macrocell24 U(0,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_9 8.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_state_0\/main_9 6.363
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_2\/main_8 8.388
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_state_2\/main_8 6.379
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 13.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.009
Route 1 Net_7 Rx(0)/fb \UART:BUART:rx_postpoll\/main_1 5.617
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.114
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.864
statusicell2 U(0,1) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.532
macrocell12 U(0,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.540
macrocell9 U(0,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.540
macrocell10 U(0,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.329
macrocell19 U(0,1) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.329
macrocell19 U(0,1) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 3.282
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.662
macrocell19 U(0,1) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.791
macrocell16 U(1,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_5 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_5 2.791
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_0\/main_5 2.793
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx(0)_PAD 31.462
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_2/main_0 3.304
macrocell1 U(0,1) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx(0)/pin_input 6.591
iocell2 P12[7] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 16.967
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000