Static Timing Analysis

Project : USB_UART
Build Time : 11/14/12 11:55:43
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 3.30
Vddd : 3.30
Vio0 : 3.30
Vio1 : 3.30
Vio2 : 3.30
Vio3 : 3.30
Voltage : 3.3
Vusb : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyPLL_OUT CyPLL_OUT 64.000 MHz 64.000 MHz N/A