Static Timing Analysis

Project : Experiment
Build Time : 10/28/15 20:16:43
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_SEQ_intClock(FFB) ADC_SAR_SEQ_intClock(FFB) 1.600 MHz 1.600 MHz N/A
Clock(FFB) Clock(FFB) 1.000 MHz 1.000 MHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
ADC_SAR_SEQ_intClock CyHFCLK 1.600 MHz 1.600 MHz N/A
Clock CyHFCLK 1.000 MHz 1.000 MHz N/A
UART_SCBCLK CyHFCLK 153.355 kHz 153.355 kHz N/A
SDCard_SD_Clock CyHFCLK 32.000 kHz 32.000 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
SDCard_SD_Clock(FFB) SDCard_SD_Clock(FFB) 32.000 kHz 32.000 kHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 153.355 kHz 153.355 kHz N/A
+ Clock To Output Section
+ CyLFCLK
Source Destination Delay (ns)
ClockBlock/lfclk LFCLK_Out(0)_PAD 20.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/lfclk 0.000
Route 1 ClockBlock_LFCLK ClockBlock/lfclk LFCLK_Out(0)/pin_input 6.545
iocell4 P1[3] 1 LFCLK_Out(0) LFCLK_Out(0)/pin_input LFCLK_Out(0)/pad_out 14.090
Route 1 LFCLK_Out(0)_PAD LFCLK_Out(0)/pad_out LFCLK_Out(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/lfclk LFCLK_Out(0)_PAD 20.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/lfclk 0.000
Route 1 ClockBlock_LFCLK ClockBlock/lfclk LFCLK_Out(0)/pin_input 6.545
iocell4 P1[3] 1 LFCLK_Out(0) LFCLK_Out(0)/pin_input LFCLK_Out(0)/pad_out 14.090
Route 1 LFCLK_Out(0)_PAD LFCLK_Out(0)/pad_out LFCLK_Out(0)_PAD 0.000
Clock Clock path delay 0.000