Static Timing Analysis

Project : SRAM_ControlReg_16Bit_Bus
Build Time : 08/29/18 11:53:04
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
VDDA : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VDDOPAMP : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 66.000 MHz 66.000 MHz N/A
Clock_1 CyMASTER_CLK 12.048  Hz 12.048  Hz 56.641 MHz
DMA_1/termout CyMASTER_CLK UNKNOWN UNKNOWN N/A
CyPLL_OUT CyPLL_OUT 66.000 MHz 66.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 8.3e+007ns(12.0482  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 56.641 MHz 17.655 82999982.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 65.113 MHz 15.358 82999984.642
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.588
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_842/main_1 87.017 MHz 11.492 82999988.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_842/main_1 2.302
macrocell3 U(0,5) 1 Net_842 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 118.821 MHz 8.416 82999991.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.580
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.326
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_842/main_0 136.240 MHz 7.340 82999992.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_842/main_0 2.580
macrocell3 U(0,5) 1 Net_842 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:runmode_enable\/q Net_842/main_0 3.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_842/main_0 2.580
macrocell3 U(0,5) 1 Net_842 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.588
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,5) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.326
macrocell2 U(0,5) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_842/main_1 5.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_842/main_1 2.302
macrocell3 U(0,5) 1 Net_842 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 5.555
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.285
datapathcell1 U(0,5) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_6 Pin_1(6)_PAD 28.587
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_6 2.580
Route 1 Net_761 \Control_Reg_1:Sync:ctrl_reg\/control_6 Pin_1(6)/pin_input 10.256
iocell15 P4[6] 1 Pin_1(6) Pin_1(6)/pin_input Pin_1(6)/pad_out 15.751
Route 1 Pin_1(6)_PAD Pin_1(6)/pad_out Pin_1(6)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_1(5)_PAD 28.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_760 \Control_Reg_1:Sync:ctrl_reg\/control_5 Pin_1(5)/pin_input 10.313
iocell14 P4[5] 1 Pin_1(5) Pin_1(5)/pin_input Pin_1(5)/pad_out 15.645
Route 1 Pin_1(5)_PAD Pin_1(5)/pad_out Pin_1(5)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_1(4)_PAD 28.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_759 \Control_Reg_1:Sync:ctrl_reg\/control_4 Pin_1(4)/pin_input 9.911
iocell13 P4[4] 1 Pin_1(4) Pin_1(4)/pin_input Pin_1(4)/pad_out 16.042
Route 1 Pin_1(4)_PAD Pin_1(4)/pad_out Pin_1(4)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_7 Pin_1(7)_PAD 28.109
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_7 2.580
Route 1 Net_762 \Control_Reg_1:Sync:ctrl_reg\/control_7 Pin_1(7)/pin_input 9.567
iocell16 P4[7] 1 Pin_1(7) Pin_1(7)/pin_input Pin_1(7)/pad_out 15.962
Route 1 Pin_1(7)_PAD Pin_1(7)/pad_out Pin_1(7)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_1(2)_PAD 27.917
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_756 \Control_Reg_1:Sync:ctrl_reg\/control_2 Pin_1(2)/pin_input 9.717
iocell11 P4[2] 1 Pin_1(2) Pin_1(2)/pin_input Pin_1(2)/pad_out 15.620
Route 1 Pin_1(2)_PAD Pin_1(2)/pad_out Pin_1(2)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_1(1)_PAD 27.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_755 \Control_Reg_1:Sync:ctrl_reg\/control_1 Pin_1(1)/pin_input 9.686
iocell10 P4[1] 1 Pin_1(1) Pin_1(1)/pin_input Pin_1(1)/pad_out 15.606
Route 1 Pin_1(1)_PAD Pin_1(1)/pad_out Pin_1(1)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_1(3)_PAD 27.698
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_757 \Control_Reg_1:Sync:ctrl_reg\/control_3 Pin_1(3)/pin_input 9.708
iocell12 P4[3] 1 Pin_1(3) Pin_1(3)/pin_input Pin_1(3)/pad_out 15.410
Route 1 Pin_1(3)_PAD Pin_1(3)/pad_out Pin_1(3)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_1(0)_PAD 27.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_758 \Control_Reg_1:Sync:ctrl_reg\/control_0 Pin_1(0)/pin_input 9.726
iocell9 P4[0] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.150
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_6 Pin_2(6)_PAD 24.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_6 2.580
Route 1 Net_771 \Control_Reg_2:Sync:ctrl_reg\/control_6 Pin_2(6)/pin_input 6.109
iocell7 P5[6] 1 Pin_2(6) Pin_2(6)/pin_input Pin_2(6)/pad_out 15.877
Route 1 Pin_2(6)_PAD Pin_2(6)/pad_out Pin_2(6)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_3 Pin_2(3)_PAD 24.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_767 \Control_Reg_2:Sync:ctrl_reg\/control_3 Pin_2(3)/pin_input 6.140
iocell4 P5[3] 1 Pin_2(3) Pin_2(3)/pin_input Pin_2(3)/pad_out 15.770
Route 1 Pin_2(3)_PAD Pin_2(3)/pad_out Pin_2(3)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_5 Pin_2(5)_PAD 24.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_770 \Control_Reg_2:Sync:ctrl_reg\/control_5 Pin_2(5)/pin_input 6.145
iocell6 P5[5] 1 Pin_2(5) Pin_2(5)/pin_input Pin_2(5)/pad_out 15.595
Route 1 Pin_2(5)_PAD Pin_2(5)/pad_out Pin_2(5)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_7 Pin_2(7)_PAD 24.305
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_7 2.580
Route 1 Net_772 \Control_Reg_2:Sync:ctrl_reg\/control_7 Pin_2(7)/pin_input 6.148
iocell8 P5[7] 1 Pin_2(7) Pin_2(7)/pin_input Pin_2(7)/pad_out 15.577
Route 1 Pin_2(7)_PAD Pin_2(7)/pad_out Pin_2(7)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_2 Pin_2(2)_PAD 23.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_766 \Control_Reg_2:Sync:ctrl_reg\/control_2 Pin_2(2)/pin_input 5.345
iocell3 P5[2] 1 Pin_2(2) Pin_2(2)/pin_input Pin_2(2)/pad_out 16.001
Route 1 Pin_2(2)_PAD Pin_2(2)/pad_out Pin_2(2)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_0 Pin_2(0)_PAD 23.365
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_768 \Control_Reg_2:Sync:ctrl_reg\/control_0 Pin_2(0)/pin_input 5.336
iocell1 P5[0] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.449
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_4 Pin_2(4)_PAD 23.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_769 \Control_Reg_2:Sync:ctrl_reg\/control_4 Pin_2(4)/pin_input 5.314
iocell5 P5[4] 1 Pin_2(4) Pin_2(4)/pin_input Pin_2(4)/pad_out 15.356
Route 1 Pin_2(4)_PAD Pin_2(4)/pad_out Pin_2(4)_PAD 0.000
Clock Clock path delay 0.000
\Control_Reg_2:Sync:ctrl_reg\/control_1 Pin_2(1)_PAD 22.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \Control_Reg_2:Sync:ctrl_reg\ \Control_Reg_2:Sync:ctrl_reg\/busclk \Control_Reg_2:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_765 \Control_Reg_2:Sync:ctrl_reg\/control_1 Pin_2(1)/pin_input 5.369
iocell2 P5[1] 1 Pin_2(1) Pin_2(1)/pin_input Pin_2(1)/pad_out 14.877
Route 1 Pin_2(1)_PAD Pin_2(1)/pad_out Pin_2(1)_PAD 0.000
Clock Clock path delay 0.000
+ DMA_1/termout
Source Destination Delay (ns)
Net_854/q P6_0(0)_PAD 37.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,5) 1 Net_854 Net_854/clock_0 Net_854/q 1.250
Route 1 Net_854 Net_854/q P6_0(0)/pin_input 5.450
iocell24 P6[0] 1 P6_0(0) P6_0(0)/pin_input P6_0(0)/pad_out 15.692
Route 1 P6_0(0)_PAD P6_0(0)/pad_out P6_0(0)_PAD 0.000
Clock Clock path delay 14.897