Static Timing Analysis

Project : Filter_SampleProject
Build Time : 06/04/12 10:47:53
Device : CY8C3866AXI-040
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk Sync 6.600 MHz 6.600 MHz N/A
ADC_DelSig_theACLK Sync 1.610 MHz 1.610 MHz N/A
ClockBlock/aclk_0 Async 1.610 MHz 1.610 MHz N/A
ClockBlock/clk_bus Async 66.000 MHz 66.000 MHz N/A
ClockBlock/dclk_0 Async 6.600 MHz 6.600 MHz N/A
ClockBlock/dclk_1 Async 100.000 kHz 100.000 kHz N/A
CyBUS_CLK Sync 66.000 MHz 66.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 66.000 MHz 66.000 MHz N/A
CyPLL_OUT Async 66.000 MHz 66.000 MHz N/A
WaveDAC8_DacClk Sync 100.000 kHz 100.000 kHz N/A