Static Timing Analysis

Project : first_ledchaser
Build Time : 05/20/15 10:31:02
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
Clock_1(routed) Clock_1
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_1(routed) Clock_1(routed) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 24.000 MHz 24.000 MHz 38.280 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:sT16:timerdp:u1\/ci 38.280 MHz 26.123 15.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \Timer:TimerUDB:control_4\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:trig_reg\/main_0 2.625
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_0 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.768
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:sT16:timerdp:u1\/ci 40.066 MHz 24.959 16.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,3) 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/clock_0 \Timer:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:trig_reg\/main_2 2.791
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_2 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.768
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:sT16:timerdp:u1\/ci 40.866 MHz 24.470 17.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/clock_0 \Timer:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:trig_reg\/main_1 2.302
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_1 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.768
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/ci 42.595 MHz 23.477 18.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.z0__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/z0 \Timer:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/z0i \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.397
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 43.739 MHz 22.863 18.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \Timer:TimerUDB:control_4\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:trig_reg\/main_0 2.625
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_0 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.788
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 43.777 MHz 22.843 18.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \Timer:TimerUDB:control_4\ \Timer:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \Timer:TimerUDB:trig_reg\/main_0 2.625
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_0 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.768
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u1\/ci 45.358 MHz 22.047 19.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ \Timer:TimerUDB:sT16:timerdp:u1\/clock \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \Timer:TimerUDB:per_zero\ \Timer:TimerUDB:sT16:timerdp:u1\/z0_comb \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.397
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 46.085 MHz 21.699 19.968
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,3) 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/clock_0 \Timer:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:trig_reg\/main_2 2.791
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_2 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.788
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 46.128 MHz 21.679 19.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,3) 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/clock_0 \Timer:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \Timer:TimerUDB:trig_rise_detected\ \Timer:TimerUDB:trig_rise_detected\/q \Timer:TimerUDB:trig_reg\/main_2 2.791
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_2 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.768
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 47.148 MHz 21.210 20.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/clock_0 \Timer:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:trig_reg\/main_1 2.302
macrocell8 U(0,3) 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/main_1 \Timer:TimerUDB:trig_reg\/q 3.350
Route 1 \Timer:TimerUDB:trig_reg\ \Timer:TimerUDB:trig_reg\/q \Timer:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.788
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,3) 1 \Timer:TimerUDB:sT16:timerdp:u0\ \Timer:TimerUDB:sT16:timerdp:u0\/clock \Timer:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \Timer:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \Timer:TimerUDB:sT16:timerdp:u0\/co_msb \Timer:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(1,3) 1 \Timer:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:timer_enable\/main_2 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/clock_0 \Timer:TimerUDB:timer_enable\/q 1.250
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:timer_enable\/main_2 2.302
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:trig_disable\/main_1 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/clock_0 \Timer:TimerUDB:timer_enable\/q 1.250
Route 1 \Timer:TimerUDB:timer_enable\ \Timer:TimerUDB:timer_enable\/q \Timer:TimerUDB:trig_disable\/main_1 2.302
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:trig_fall_detected\/q \Timer:TimerUDB:trig_fall_detected\/main_3 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,3) 1 \Timer:TimerUDB:trig_fall_detected\ \Timer:TimerUDB:trig_fall_detected\/clock_0 \Timer:TimerUDB:trig_fall_detected\/q 1.250
macrocell6 U(0,3) 1 \Timer:TimerUDB:trig_fall_detected\ \Timer:TimerUDB:trig_fall_detected\/q \Timer:TimerUDB:trig_fall_detected\/main_3 2.303
macrocell6 U(0,3) 1 \Timer:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:trig_disable\/q \Timer:TimerUDB:timer_enable\/main_5 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ \Timer:TimerUDB:trig_disable\/clock_0 \Timer:TimerUDB:trig_disable\/q 1.250
Route 1 \Timer:TimerUDB:trig_disable\ \Timer:TimerUDB:trig_disable\/q \Timer:TimerUDB:timer_enable\/main_5 2.314
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:trig_disable\/q \Timer:TimerUDB:trig_disable\/main_4 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ \Timer:TimerUDB:trig_disable\/clock_0 \Timer:TimerUDB:trig_disable\/q 1.250
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ \Timer:TimerUDB:trig_disable\/q \Timer:TimerUDB:trig_disable\/main_4 2.314
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:run_mode\/q \Timer:TimerUDB:timer_enable\/main_3 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/clock_0 \Timer:TimerUDB:run_mode\/q 1.250
Route 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/q \Timer:TimerUDB:timer_enable\/main_3 2.581
macrocell4 U(0,3) 1 \Timer:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:run_mode\/q \Timer:TimerUDB:trig_disable\/main_2 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/clock_0 \Timer:TimerUDB:run_mode\/q 1.250
Route 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/q \Timer:TimerUDB:trig_disable\/main_2 2.581
macrocell5 U(0,3) 1 \Timer:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:run_mode\/q Net_130/main_1 3.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,3) 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/clock_0 \Timer:TimerUDB:run_mode\/q 1.250
Route 1 \Timer:TimerUDB:run_mode\ \Timer:TimerUDB:run_mode\/q Net_130/main_1 2.583
macrocell1 U(0,3) 1 Net_130 HOLD 0.000
Clock Skew 0.000
\Timer:TimerUDB:trig_last\/q \Timer:TimerUDB:trig_rise_detected\/main_2 4.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,3) 1 \Timer:TimerUDB:trig_last\ \Timer:TimerUDB:trig_last\/clock_0 \Timer:TimerUDB:trig_last\/q 1.250
Route 1 \Timer:TimerUDB:trig_last\ \Timer:TimerUDB:trig_last\/q \Timer:TimerUDB:trig_rise_detected\/main_2 2.769
macrocell9 U(0,3) 1 \Timer:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
+ Asynchronous Clock Crossing Section
+ Source Clock Clock_1(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 \Timer:TimerUDB:trig_last\/main_0 12.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_10_local ClockBlock/dclk_0 \Timer:TimerUDB:trig_last\/main_0 8.543
macrocell7 U(1,3) 1 \Timer:TimerUDB:trig_last\ SETUP 3.510
Clock Skew 0.000
ClockBlock/dclk_0 \Timer:TimerUDB:trig_fall_detected\/main_4 12.031
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_10_local ClockBlock/dclk_0 \Timer:TimerUDB:trig_fall_detected\/main_4 8.521
macrocell6 U(0,3) 1 \Timer:TimerUDB:trig_fall_detected\ SETUP 3.510
Clock Skew 0.000
ClockBlock/dclk_0 \Timer:TimerUDB:trig_rise_detected\/main_4 12.022
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_10_local ClockBlock/dclk_0 \Timer:TimerUDB:trig_rise_detected\/main_4 8.512
macrocell9 U(0,3) 1 \Timer:TimerUDB:trig_rise_detected\ SETUP 3.510
Clock Skew 0.000