Static Timing Analysis

Project : SPI_Bootloader_Host
Build Time : 10/07/14 13:49:24
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
SPIM_IntClock CyMASTER_CLK 2.000 MHz 2.000 MHz 61.660 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:RxStsReg\/status_6 61.660 MHz 16.218 483.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \SPIM:BSPIM:rx_status_4\ \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:rx_status_6\/main_5 3.764
macrocell8 U(0,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_5 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.254
statusicell1 U(1,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:sR8:Dp:u0\/so_comb Net_154/main_4 70.741 MHz 14.136 485.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM:BSPIM:mosi_from_dp\ \SPIM:BSPIM:sR8:Dp:u0\/so_comb Net_154/main_4 2.326
macrocell1 U(0,1) 1 Net_154 SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:TxStsReg\/status_3 71.989 MHz 13.891 486.109
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 3.699
macrocell7 U(0,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.162
statusicell2 U(0,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:RxStsReg\/status_6 74.344 MHz 13.451 486.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:rx_status_6\/main_2 4.167
macrocell8 U(0,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_2 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.254
statusicell1 U(1,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 74.996 MHz 13.334 486.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 2.110
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 3.142
macrocell7 U(0,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.162
statusicell2 U(0,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 75.086 MHz 13.318 486.682
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 3.699
macrocell7 U(0,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 2.309
datapathcell1 U(0,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:TxStsReg\/status_0 75.815 MHz 13.190 486.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:tx_status_0\/main_0 4.147
macrocell12 U(0,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_0 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 2.873
statusicell2 U(0,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:RxStsReg\/status_6 76.161 MHz 13.130 486.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 2.110
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:rx_status_6\/main_4 3.846
macrocell8 U(0,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_4 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.254
statusicell1 U(1,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 76.758 MHz 13.028 486.972
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 2.110
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.836
macrocell7 U(0,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 3.162
statusicell2 U(0,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:RxStsReg\/status_6 76.876 MHz 13.008 486.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 2.110
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:rx_status_6\/main_0 3.724
macrocell8 U(0,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_0 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.254
statusicell1 U(1,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_193/q Net_193/main_3 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 Net_193 Net_193/clock_0 Net_193/q 1.250
macrocell3 U(1,0) 1 Net_193 Net_193/q Net_193/main_3 2.228
macrocell3 U(1,0) 1 Net_193 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell6 U(0,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.235
macrocell6 U(0,0) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 3.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
macrocell4 U(0,0) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 2.514
macrocell4 U(0,0) 1 \SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q Net_154/main_10 3.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q Net_154/main_10 2.600
macrocell1 U(0,1) 1 Net_154 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 2.601
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 2.601
macrocell10 U(0,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_2\/main_9 3.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_2\/main_9 2.601
macrocell11 U(0,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_1\/q \SPIM:BSPIM:state_0\/main_1 4.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q \SPIM:BSPIM:state_0\/main_1 3.123
macrocell9 U(1,1) 1 \SPIM:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
Net_155/q Net_155/main_0 4.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,0) 1 Net_155 Net_155/clock_0 Net_155/q 1.250
macrocell2 U(0,0) 1 Net_155 Net_155/q Net_155/main_0 3.309
macrocell2 U(0,0) 1 Net_155 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 4.562
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,0) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
Route 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 3.312
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 20.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell1 P5[3] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 7.832
Route 1 Net_157 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 6.170
datapathcell1 U(0,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
Net_154/q MOSI(0)_PAD 22.897
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,1) 1 Net_154 Net_154/clock_0 Net_154/q 1.250
Route 1 Net_154 Net_154/q MOSI(0)/pin_input 6.793
iocell2 P5[1] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 14.854
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_155/q SCLK(0)_PAD 22.310
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,0) 1 Net_155 Net_155/clock_0 Net_155/q 1.250
Route 1 Net_155 Net_155/q SCLK(0)/pin_input 6.670
iocell4 P5[5] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 14.390
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000