Static Timing Analysis

Project : Filter_ADC_VDAC02works27.3_Copy_02
Build Time : 05/20/15 17:34:19
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_DelSig_theACLK(fixed-function) ADC_DelSig_theACLK(fixed-function) 380.952 kHz 380.952 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_DelSig_theACLK CyMASTER_CLK 380.952 kHz 380.952 kHz N/A
DVDAC_1_IntClock CyMASTER_CLK 250.000 kHz 250.000 kHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
DVDAC_1_IntClock(routed) DVDAC_1_IntClock(routed) 250.000 kHz 250.000 kHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A