Static Timing Analysis

Project : Lession3
Build Time : 08/11/20 17:56:44
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 59.025 MHz
UART_IntClock CyMASTER_CLK 153.846 kHz 153.846 kHz 51.848 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_2(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 59.025 MHz 16.942 24.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_postpoll\/main_0 5.038
macrocell6 U(3,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_state_2\/main_0 86.029 MHz 11.624 30.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_state_2\/main_0 5.931
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_last\/main_0 86.949 MHz 11.501 30.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_last\/main_0 5.808
macrocell24 U(3,3) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:pollcount_1\/main_0 87.009 MHz 11.493 30.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:pollcount_1\/main_0 5.800
macrocell21 U(3,5) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:pollcount_0\/main_0 87.009 MHz 11.493 30.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:pollcount_0\/main_0 5.800
macrocell22 U(3,5) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_state_0\/main_0 93.188 MHz 10.731 30.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_state_0\/main_0 5.038
macrocell15 U(3,4) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_status_3\/main_0 93.188 MHz 10.731 30.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_status_3\/main_0 5.038
macrocell23 U(3,4) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 6500ns(153.846 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 51.848 MHz 19.287 6480.713
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 5.578
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 52.282 MHz 19.127 6480.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,4) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 6.843
macrocell5 U(2,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.324
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 53.996 MHz 18.520 6481.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,5) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 4.811
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.426 MHz 18.042 6481.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,5) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.333
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.793 MHz 17.303 6482.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.654
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 58.545 MHz 17.081 6482.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,4) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 4.797
macrocell5 U(2,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.324
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxShifter:u0\/cs_addr_2 58.987 MHz 16.953 6483.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,4) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxShifter:u0\/cs_addr_2 9.693
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 61.166 MHz 16.349 6483.651
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.065
macrocell5 U(2,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.324
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 65.117 MHz 15.357 6484.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.073
macrocell5 U(2,3) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.324
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 69.565 MHz 14.375 6485.625
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,5) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 3.404
macrocell6 U(3,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_2(0)/fb \UART:BUART:rx_state_0\/main_0 7.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_state_0\/main_0 5.038
macrocell15 U(3,4) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_status_3\/main_0 7.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_status_3\/main_0 5.038
macrocell23 U(3,4) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:pollcount_1\/main_0 7.983
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:pollcount_1\/main_0 5.800
macrocell21 U(3,5) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:pollcount_0\/main_0 7.983
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:pollcount_0\/main_0 5.800
macrocell22 U(3,5) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_last\/main_0 7.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_last\/main_0 5.808
macrocell24 U(3,3) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:rx_state_2\/main_0 8.114
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_state_2\/main_0 5.931
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 13.472
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[0] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.183
Route 1 Net_105 Rx_2(0)/fb \UART:BUART:rx_postpoll\/main_0 5.038
macrocell6 U(3,4) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.901
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,4) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.306
statusicell2 U(3,4) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.326
macrocell19 U(3,3) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 3.280
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.660
macrocell19 U(3,3) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 3.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.665
macrocell19 U(3,3) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 3.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,5) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 3.108
datapathcell1 U(3,5) 1 \UART:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 3.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 2.798
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 2.800
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 3.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 2.803
macrocell18 U(3,3) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 3.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 2.816
macrocell16 U(2,3) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 3.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.822
macrocell16 U(2,3) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_2(0)_PAD 27.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_100/main_0 2.582
macrocell1 U(3,5) 1 Net_100 Net_100/main_0 Net_100/q 3.350
Route 1 Net_100 Net_100/q Tx_2(0)/pin_input 5.581
iocell4 P4[7] 1 Tx_2(0) Tx_2(0)/pin_input Tx_2(0)/pad_out 15.222
Route 1 Tx_2(0)_PAD Tx_2(0)/pad_out Tx_2(0)_PAD 0.000
Clock Clock path delay 0.000