Static Timing Analysis

Project : USBFS_Bootloader01
Build Time : 09/07/16 11:29:53
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 48.000 MHz 48.000 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz 145.624 MHz
I2C_IntClock CyMASTER_CLK 1.600 MHz 1.600 MHz 36.130 MHz
Clock_1 CyMASTER_CLK 100.000  Hz 100.000  Hz 90.123 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
CyScBoostClk CyScBoostClk 9.600 MHz 9.600 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1e+007ns(100  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 90.123 MHz 11.096 9999988.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.634
macrocell2 U(2,1) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.322
statusicell1 U(2,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 91.191 MHz 10.966 9999989.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.616
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 99.880 MHz 10.012 9999989.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.590
macrocell2 U(2,1) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.322
statusicell1 U(2,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 100.878 MHz 9.913 9999990.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.603
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_1 119.660 MHz 8.357 9999991.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_1 2.337
macrocell11 U(2,1) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_2 119.660 MHz 8.357 9999991.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_2 2.337
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_126/main_2 119.660 MHz 8.357 9999991.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_126/main_2 2.337
macrocell14 U(2,1) 1 Net_126 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 122.895 MHz 8.137 9999991.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 2.300
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.327
macrocell11 U(2,1) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:status_0\/main_1 122.895 MHz 8.137 9999991.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 2.300
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:status_0\/main_1 2.327
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_126/main_1 122.895 MHz 8.137 9999991.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 2.300
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_126/main_1 2.327
macrocell14 U(2,1) 1 Net_126 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
SDA(0)_SYNC/out \I2C:bI2C_UDB:sda_in_reg\/main_0 145.624 MHz 6.867 13.966
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,5) 1 SDA(0)_SYNC SDA(0)_SYNC/clock SDA(0)_SYNC/out 1.020
Route 1 \I2C:Net_1109_1_SYNCOUT\ SDA(0)_SYNC/out \I2C:bI2C_UDB:sda_in_reg\/main_0 2.337
macrocell15 U(2,5) 1 \I2C:bI2C_UDB:sda_in_reg\ SETUP 3.510
Clock Skew 0.000
SDA(0)_SYNC/out \I2C:bI2C_UDB:status_1\/main_8 145.624 MHz 6.867 13.966
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,5) 1 SDA(0)_SYNC SDA(0)_SYNC/clock SDA(0)_SYNC/out 1.020
Route 1 \I2C:Net_1109_1_SYNCOUT\ SDA(0)_SYNC/out \I2C:bI2C_UDB:status_1\/main_8 2.337
macrocell23 U(2,5) 1 \I2C:bI2C_UDB:status_1\ SETUP 3.510
Clock Skew 0.000
SCL(0)_SYNC/out \I2C:bI2C_UDB:scl_in_reg\/main_0 145.794 MHz 6.859 13.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 SCL(0)_SYNC SCL(0)_SYNC/clock SCL(0)_SYNC/out 1.020
Route 1 \I2C:Net_1109_0_SYNCOUT\ SCL(0)_SYNC/out \I2C:bI2C_UDB:scl_in_reg\/main_0 2.329
macrocell25 U(2,1) 1 \I2C:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Skew 0.000
SCL(0)_SYNC/out \I2C:bI2C_UDB:clk_eq_reg\/main_1 145.794 MHz 6.859 13.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 SCL(0)_SYNC SCL(0)_SYNC/clock SCL(0)_SYNC/out 1.020
Route 1 \I2C:Net_1109_0_SYNCOUT\ SCL(0)_SYNC/out \I2C:bI2C_UDB:clk_eq_reg\/main_1 2.329
macrocell35 U(2,1) 1 \I2C:bI2C_UDB:clk_eq_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 625ns(1.6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 36.130 MHz 27.678 597.322
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,5) 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/clock_0 \I2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:cnt_reset\/main_3 8.185
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_3 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 2.601
macrocell9 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 2.932
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 38.024 MHz 26.299 598.701
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,5) 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/clock_0 \I2C:bI2C_UDB:m_state_3\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:cnt_reset\/main_1 6.806
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_1 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 2.601
macrocell9 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 2.932
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 39.719 MHz 25.177 599.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,5) 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/clock_0 \I2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:cnt_reset\/main_3 8.185
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_3 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 2.601
macrocell6 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 \I2C:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.311
datapathcell3 U(2,3) 1 \I2C:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_1 40.334 MHz 24.793 600.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,3) 1 \I2C:bI2C_UDB:m_state_0\ \I2C:bI2C_UDB:m_state_0\/clock_0 \I2C:bI2C_UDB:m_state_0\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_0\ \I2C:bI2C_UDB:m_state_0\/q \I2C:bI2C_UDB:cs_addr_shifter_1\/main_5 10.979
macrocell8 U(3,5) 1 \I2C:bI2C_UDB:cs_addr_shifter_1\ \I2C:bI2C_UDB:cs_addr_shifter_1\/main_5 \I2C:bI2C_UDB:cs_addr_shifter_1\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_1\ \I2C:bI2C_UDB:cs_addr_shifter_1\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_1 3.204
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_2\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 41.570 MHz 24.056 600.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,4) 1 \I2C:bI2C_UDB:m_state_2\ \I2C:bI2C_UDB:m_state_2\/clock_0 \I2C:bI2C_UDB:m_state_2\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_2\ \I2C:bI2C_UDB:m_state_2\/q \I2C:bI2C_UDB:cnt_reset\/main_2 4.563
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_2 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 2.601
macrocell9 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 2.932
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 41.976 MHz 23.823 601.177
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,3) 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/clock_0 \I2C:bI2C_UDB:clkgen_tc1_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:clkgen_tc1_reg\ \I2C:bI2C_UDB:clkgen_tc1_reg\/q \I2C:bI2C_UDB:cnt_reset\/main_7 4.330
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_7 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 2.601
macrocell9 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 2.932
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 42.020 MHz 23.798 601.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,5) 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/clock_0 \I2C:bI2C_UDB:m_state_3\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_3\ \I2C:bI2C_UDB:m_state_3\/q \I2C:bI2C_UDB:cnt_reset\/main_1 6.806
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_1 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 2.601
macrocell6 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/main_1 \I2C:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_clkgen_1\ \I2C:bI2C_UDB:cs_addr_clkgen_1\/q \I2C:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.311
datapathcell3 U(2,3) 1 \I2C:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:m_state_4\/main_6 42.150 MHz 23.725 601.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,5) 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/clock_0 \I2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:m_state_4_split\/main_7 11.212
macrocell1 U(3,1) 1 \I2C:bI2C_UDB:m_state_4_split\ \I2C:bI2C_UDB:m_state_4_split\/main_7 \I2C:bI2C_UDB:m_state_4_split\/q 3.350
Route 1 \I2C:bI2C_UDB:m_state_4_split\ \I2C:bI2C_UDB:m_state_4_split\/q \I2C:bI2C_UDB:m_state_4\/main_6 4.403
macrocell16 U(3,4) 1 \I2C:bI2C_UDB:m_state_4\ SETUP 3.510
Clock Skew 0.000
\I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:m_state_0\/main_8 42.510 MHz 23.524 601.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,5) 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/clock_0 \I2C:bI2C_UDB:m_state_1\/q 1.250
Route 1 \I2C:bI2C_UDB:m_state_1\ \I2C:bI2C_UDB:m_state_1\/q \I2C:bI2C_UDB:m_state_0_split\/main_7 11.768
macrocell13 U(3,1) 1 \I2C:bI2C_UDB:m_state_0_split\ \I2C:bI2C_UDB:m_state_0_split\/main_7 \I2C:bI2C_UDB:m_state_0_split\/q 3.350
Route 1 \I2C:bI2C_UDB:m_state_0_split\ \I2C:bI2C_UDB:m_state_0_split\/q \I2C:bI2C_UDB:m_state_0\/main_8 3.646
macrocell20 U(3,3) 1 \I2C:bI2C_UDB:m_state_0\ SETUP 3.510
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 42.640 MHz 23.452 601.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/clock_0 \I2C:bI2C_UDB:scl_in_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:cnt_reset\/main_5 3.959
macrocell5 U(2,3) 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/main_5 \I2C:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2C:bI2C_UDB:cnt_reset\ \I2C:bI2C_UDB:cnt_reset\/q \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 2.601
macrocell9 U(2,3) 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2C:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2C:bI2C_UDB:cs_addr_shifter_0\ \I2C:bI2C_UDB:cs_addr_shifter_0\/q \I2C:bI2C_UDB:Shifter:u0\/cs_addr_0 2.932
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.577
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.327
statusicell1 U(2,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 0.720
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.327
macrocell11 U(2,1) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:status_0\/main_1 3.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 0.720
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb \PWM_1:PWMUDB:status_0\/main_1 2.327
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_126/main_1 3.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb 0.720
Route 1 \PWM_1:PWMUDB:cmp1_eq\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/ce0_comb Net_126/main_1 2.327
macrocell14 U(2,1) 1 Net_126 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_1 3.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_1 2.337
macrocell11 U(2,1) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_2 3.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_2 2.337
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_126/main_2 3.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_126/main_2 2.337
macrocell14 U(2,1) 1 Net_126 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,1) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.300
macrocell12 U(2,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_126/main_0 3.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_126/main_0 2.590
macrocell14 U(2,1) 1 Net_126 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.853
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.603
datapathcell1 U(2,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
SCL(0)_SYNC/out \I2C:bI2C_UDB:scl_in_reg\/main_0 2.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 SCL(0)_SYNC SCL(0)_SYNC/clock SCL(0)_SYNC/out 0.350
Route 1 \I2C:Net_1109_0_SYNCOUT\ SCL(0)_SYNC/out \I2C:bI2C_UDB:scl_in_reg\/main_0 2.329
macrocell25 U(2,1) 1 \I2C:bI2C_UDB:scl_in_reg\ HOLD 0.000
Clock Skew 0.000
SCL(0)_SYNC/out \I2C:bI2C_UDB:clk_eq_reg\/main_1 2.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 SCL(0)_SYNC SCL(0)_SYNC/clock SCL(0)_SYNC/out 0.350
Route 1 \I2C:Net_1109_0_SYNCOUT\ SCL(0)_SYNC/out \I2C:bI2C_UDB:clk_eq_reg\/main_1 2.329
macrocell35 U(2,1) 1 \I2C:bI2C_UDB:clk_eq_reg\ HOLD 0.000
Clock Skew 0.000
SDA(0)_SYNC/out \I2C:bI2C_UDB:sda_in_reg\/main_0 2.687
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,5) 1 SDA(0)_SYNC SDA(0)_SYNC/clock SDA(0)_SYNC/out 0.350
Route 1 \I2C:Net_1109_1_SYNCOUT\ SDA(0)_SYNC/out \I2C:bI2C_UDB:sda_in_reg\/main_0 2.337
macrocell15 U(2,5) 1 \I2C:bI2C_UDB:sda_in_reg\ HOLD 0.000
Clock Skew 0.000
SDA(0)_SYNC/out \I2C:bI2C_UDB:status_1\/main_8 2.687
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,5) 1 SDA(0)_SYNC SDA(0)_SYNC/clock SDA(0)_SYNC/out 0.350
Route 1 \I2C:Net_1109_1_SYNCOUT\ SDA(0)_SYNC/out \I2C:bI2C_UDB:status_1\/main_8 2.337
macrocell23 U(2,5) 1 \I2C:bI2C_UDB:status_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\I2C:bI2C_UDB:Shifter:u0\/so_comb \I2C:sda_x_wire\/main_2 3.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,4) 1 \I2C:bI2C_UDB:Shifter:u0\ \I2C:bI2C_UDB:Shifter:u0\/clock \I2C:bI2C_UDB:Shifter:u0\/so_comb 0.800
Route 1 \I2C:bI2C_UDB:shift_data_out\ \I2C:bI2C_UDB:Shifter:u0\/so_comb \I2C:sda_x_wire\/main_2 2.298
macrocell37 U(3,4) 1 \I2C:sda_x_wire\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2C:bI2C_UDB:m_state_3\/main_2 3.263
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 0.360
Route 1 \I2C:bI2C_UDB:control_2\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2C:bI2C_UDB:m_state_3\/main_2 2.903
macrocell17 U(3,5) 1 \I2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 \I2C:bI2C_UDB:m_reset\/main_0 3.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 0.360
Route 1 \I2C:bI2C_UDB:control_1\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_1 \I2C:bI2C_UDB:m_reset\/main_0 2.931
macrocell38 U(3,3) 1 \I2C:bI2C_UDB:m_reset\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \I2C:bI2C_UDB:m_state_3\/main_1 3.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \I2C:bI2C_UDB:SyncCtl:CtrlReg\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 0.360
Route 1 \I2C:bI2C_UDB:control_5\ \I2C:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \I2C:bI2C_UDB:m_state_3\/main_1 3.058
macrocell17 U(3,5) 1 \I2C:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:sda_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_4 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(2,4) 1 \I2C:bI2C_UDB:sda_in_last2_reg\ \I2C:bI2C_UDB:sda_in_last2_reg\/clock_0 \I2C:bI2C_UDB:sda_in_last2_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:sda_in_last2_reg\ \I2C:bI2C_UDB:sda_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_4 2.289
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:bus_busy_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_6 3.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ \I2C:bI2C_UDB:bus_busy_reg\/clock_0 \I2C:bI2C_UDB:bus_busy_reg\/q 1.250
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ \I2C:bI2C_UDB:bus_busy_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_6 2.296
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:sda_in_last_reg\/q \I2C:bI2C_UDB:sda_in_last2_reg\/main_0 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \I2C:bI2C_UDB:sda_in_last_reg\ \I2C:bI2C_UDB:sda_in_last_reg\/clock_0 \I2C:bI2C_UDB:sda_in_last_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:sda_in_last_reg\ \I2C:bI2C_UDB:sda_in_last_reg\/q \I2C:bI2C_UDB:sda_in_last2_reg\/main_0 2.299
macrocell29 U(2,4) 1 \I2C:bI2C_UDB:sda_in_last2_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:sda_in_last_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_3 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(2,4) 1 \I2C:bI2C_UDB:sda_in_last_reg\ \I2C:bI2C_UDB:sda_in_last_reg\/clock_0 \I2C:bI2C_UDB:sda_in_last_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:sda_in_last_reg\ \I2C:bI2C_UDB:sda_in_last_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_3 2.299
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_2 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,4) 1 \I2C:bI2C_UDB:scl_in_last2_reg\ \I2C:bI2C_UDB:scl_in_last2_reg\/clock_0 \I2C:bI2C_UDB:scl_in_last2_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_last2_reg\ \I2C:bI2C_UDB:scl_in_last2_reg\/q \I2C:bI2C_UDB:bus_busy_reg\/main_2 2.301
macrocell34 U(2,4) 1 \I2C:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:scl_in_last_reg\/main_0 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/clock_0 \I2C:bI2C_UDB:scl_in_reg\/q 1.250
Route 1 \I2C:bI2C_UDB:scl_in_reg\ \I2C:bI2C_UDB:scl_in_reg\/q \I2C:bI2C_UDB:scl_in_last_reg\/main_0 2.311
macrocell26 U(2,1) 1 \I2C:bI2C_UDB:scl_in_last_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_126/q LED4(0)_PAD 23.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,1) 1 Net_126 Net_126/clock_0 Net_126/q 1.250
Route 1 Net_126 Net_126/q LED4(0)/pin_input 7.106
iocell3 P1[7] 1 LED4(0) LED4(0)/pin_input LED4(0)/pad_out 15.381
Route 1 LED4(0)_PAD LED4(0)/pad_out LED4(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C_1:I2C_FF\/sda_out SDA_1(0)_PAD:out 27.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/sda_out 1.000
Route 1 \I2C_1:sda_x_wire\ \I2C_1:I2C_FF\/sda_out SDA_1(0)/pin_input 10.192
iocell1 P4[6] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 15.976
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_1:I2C_FF\/scl_out SCL_1(0)_PAD:out 24.860
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/scl_out 1.000
Route 1 \I2C_1:Net_643_0\ \I2C_1:I2C_FF\/scl_out SCL_1(0)/pin_input 8.980
iocell2 P0[4] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 14.880
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ I2C_IntClock
Source Destination Delay (ns)
\I2C:sda_x_wire\/q SDA(0)_PAD:out 23.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,4) 1 \I2C:sda_x_wire\ \I2C:sda_x_wire\/clock_0 \I2C:sda_x_wire\/q 1.250
Route 1 \I2C:sda_x_wire\ \I2C:sda_x_wire\/q SDA(0)/pin_input 6.669
iocell6 P0[1] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 15.802
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:Net_643_3\/q SCL(0)_PAD:out 23.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,3) 1 \I2C:Net_643_3\ \I2C:Net_643_3\/clock_0 \I2C:Net_643_3\/q 1.250
Route 1 \I2C:Net_643_3\ \I2C:Net_643_3\/q SCL(0)/pin_input 7.708
iocell7 P15[0] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 14.255
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000