Static Timing Analysis

Project : two_independent_window_SCA
Build Time : 05/08/14 11:08:40
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_3(routed) Clock_3(routed) 11.999  Hz 11.999  Hz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_3 CyMASTER_CLK 11.999  Hz 11.999  Hz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 38.634 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_SCA_2_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 38.634 MHz 25.884 15.783
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_2_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_2_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter_SCA_2_S1:CounterUDB:control_7\ \Counter_SCA_2_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_2_S1:CounterUDB:count_enable\/main_1 2.342
macrocell13 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:count_enable\ \Counter_SCA_2_S1:CounterUDB:count_enable\/main_1 \Counter_SCA_2_S1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_2_S1:CounterUDB:count_enable\ \Counter_SCA_2_S1:CounterUDB:count_enable\/q \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.802
datapathcell5 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_1_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 38.685 MHz 25.850 15.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_1_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_1_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter_SCA_1_S2:CounterUDB:control_7\ \Counter_SCA_1_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_1_S2:CounterUDB:count_enable\/main_1 2.342
macrocell7 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:count_enable\ \Counter_SCA_1_S2:CounterUDB:count_enable\/main_1 \Counter_SCA_1_S2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_1_S2:CounterUDB:count_enable\ \Counter_SCA_1_S2:CounterUDB:count_enable\/q \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell3 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell4 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 38.921 MHz 25.693 15.974
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter_SCA_2_S2:CounterUDB:control_7\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_2_S2:CounterUDB:count_enable\/main_1 2.342
macrocell19 U(3,4) 1 \Counter_SCA_2_S2:CounterUDB:count_enable\ \Counter_SCA_2_S2:CounterUDB:count_enable\/main_1 \Counter_SCA_2_S2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_2_S2:CounterUDB:count_enable\ \Counter_SCA_2_S2:CounterUDB:count_enable\/q \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.611
datapathcell7 U(3,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell8 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 38.926 MHz 25.690 15.977
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter_SCA_1_S1:CounterUDB:control_7\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SCA_1_S1:CounterUDB:count_enable\/main_1 2.279
macrocell1 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:count_enable\ \Counter_SCA_1_S1:CounterUDB:count_enable\/main_1 \Counter_SCA_1_S1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_1_S1:CounterUDB:count_enable\ \Counter_SCA_1_S1:CounterUDB:count_enable\/q \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.671
datapathcell1 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_2_S1:CounterUDB:count_stored_i\/q \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 40.785 MHz 24.519 17.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:count_stored_i\ \Counter_SCA_2_S1:CounterUDB:count_stored_i\/clock_0 \Counter_SCA_2_S1:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_SCA_2_S1:CounterUDB:count_stored_i\ \Counter_SCA_2_S1:CounterUDB:count_stored_i\/q \Counter_SCA_2_S1:CounterUDB:count_enable\/main_2 2.307
macrocell13 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:count_enable\ \Counter_SCA_2_S1:CounterUDB:count_enable\/main_2 \Counter_SCA_2_S1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_2_S1:CounterUDB:count_enable\ \Counter_SCA_2_S1:CounterUDB:count_enable\/q \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.802
datapathcell5 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_1_S2:CounterUDB:count_stored_i\/q \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 40.871 MHz 24.467 17.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:count_stored_i\ \Counter_SCA_1_S2:CounterUDB:count_stored_i\/clock_0 \Counter_SCA_1_S2:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_SCA_1_S2:CounterUDB:count_stored_i\ \Counter_SCA_1_S2:CounterUDB:count_stored_i\/q \Counter_SCA_1_S2:CounterUDB:count_enable\/main_2 2.289
macrocell7 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:count_enable\ \Counter_SCA_1_S2:CounterUDB:count_enable\/main_2 \Counter_SCA_1_S2:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_1_S2:CounterUDB:count_enable\ \Counter_SCA_1_S2:CounterUDB:count_enable\/q \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell3 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell4 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 40.955 MHz 24.417 17.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/ce0 3.540
Route 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0.ce0__sig\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ce0i 0.000
datapathcell4 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ce0i \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_SCA_1_S2:CounterUDB:reload\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.107
datapathcell3 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell4 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 40.989 MHz 24.397 17.270
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/ce0 3.540
Route 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0.ce0__sig\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ce0i 0.000
datapathcell8 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ce0i \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_SCA_2_S2:CounterUDB:reload\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.087
datapathcell7 U(3,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell8 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 41.002 MHz 24.389 17.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/ce0 3.540
Route 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0.ce0__sig\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ce0i 0.000
datapathcell6 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ce0i \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_SCA_2_S1:CounterUDB:reload\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.079
datapathcell5 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
\Counter_SCA_1_S1:CounterUDB:count_stored_i\/q \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 41.115 MHz 24.322 17.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:count_stored_i\ \Counter_SCA_1_S1:CounterUDB:count_stored_i\/clock_0 \Counter_SCA_1_S1:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_SCA_1_S1:CounterUDB:count_stored_i\ \Counter_SCA_1_S1:CounterUDB:count_stored_i\/q \Counter_SCA_1_S1:CounterUDB:count_enable\/main_2 2.241
macrocell1 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:count_enable\ \Counter_SCA_1_S1:CounterUDB:count_enable\/main_2 \Counter_SCA_1_S1:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SCA_1_S1:CounterUDB:count_enable\ \Counter_SCA_1_S1:CounterUDB:count_enable\/q \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.671
datapathcell1 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\ SETUP 5.100
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 3.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb 3.090
Route 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 3.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb 3.090
Route 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell4 U(3,3) 1 \Counter_SCA_1_S2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 3.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb 3.090
Route 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell6 U(0,2) 1 \Counter_SCA_2_S1:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 3.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/clock \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb 3.090
Route 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell8 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_0 4.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 2.040
Route 1 \Counter_SCA_1_S1:CounterUDB:ctrl_cmod_2\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_0 2.542
macrocell4 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_2 4.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 2.040
Route 1 \Counter_SCA_1_S1:CounterUDB:ctrl_cmod_0\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_2 2.545
macrocell4 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_2 4.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 2.040
Route 1 \Counter_SCA_2_S2:CounterUDB:ctrl_cmod_0\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_0 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_2 2.616
macrocell22 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_1 4.732
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 2.040
Route 1 \Counter_SCA_1_S1:CounterUDB:ctrl_cmod_1\ \Counter_SCA_1_S1:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 \Counter_SCA_1_S1:CounterUDB:prevCompare\/main_1 2.692
macrocell4 U(3,0) 1 \Counter_SCA_1_S1:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_0 4.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 2.040
Route 1 \Counter_SCA_2_S2:CounterUDB:ctrl_cmod_2\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_2 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_0 2.789
macrocell22 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_1 4.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 2.040
Route 1 \Counter_SCA_2_S2:CounterUDB:ctrl_cmod_1\ \Counter_SCA_2_S2:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_1 \Counter_SCA_2_S2:CounterUDB:prevCompare\/main_1 2.790
macrocell22 U(2,4) 1 \Counter_SCA_2_S2:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_3(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 Pin_test(0)_PAD 23.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_321_local ClockBlock/dclk_0 Pin_test(0)/pin_input 7.572
iocell1 P1[7] 1 Pin_test(0) Pin_test(0)/pin_input Pin_test(0)/pad_out 16.164
Route 1 Pin_test(0)_PAD Pin_test(0)/pad_out Pin_test(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 Pin_test(0)_PAD 23.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_321_local ClockBlock/dclk_0 Pin_test(0)/pin_input 7.572
iocell1 P1[7] 1 Pin_test(0) Pin_test(0)/pin_input Pin_test(0)/pad_out 16.164
Route 1 Pin_test(0)_PAD Pin_test(0)/pad_out Pin_test(0)_PAD 0.000
Clock Clock path delay 0.000