Static Timing Analysis

Project : Pulse Width Measurement
Build Time : 05/14/14 14:38:52
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ResolutionClk CyMASTER_CLK 1.000 MHz 1.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 38.742 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
ResolutionClk(routed) ResolutionClk(routed) 1.000 MHz 1.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:sC16:counterdp:u1\/ci 38.742 MHz 25.812 15.855
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter:CounterUDB:control_7\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:count_enable\/main_1 2.314
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_1 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:sC16:counterdp:u1\/ci 40.438 MHz 24.729 16.938
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_183 \Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:count_enable\/main_3 2.331
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_3 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Counter:CounterUDB:count_stored_i\/q \Counter:CounterUDB:sC16:counterdp:u1\/ci 40.890 MHz 24.456 17.211
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,3) 1 \Counter:CounterUDB:count_stored_i\ \Counter:CounterUDB:count_stored_i\/clock_0 \Counter:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter:CounterUDB:count_stored_i\ \Counter:CounterUDB:count_stored_i\/q \Counter:CounterUDB:count_enable\/main_2 2.288
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_2 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
Net_134/q \Counter:CounterUDB:sC16:counterdp:u1\/ci 40.891 MHz 24.455 17.212
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,3) 1 Net_134 Net_134/clock_0 Net_134/q 1.250
Route 1 Net_134 Net_134/q \Counter:CounterUDB:count_enable\/main_0 2.287
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_0 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 44.340 MHz 22.553 19.114
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter:CounterUDB:control_7\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:count_enable\/main_1 2.314
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_1 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.789
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 44.381 MHz 22.532 19.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,3) 1 \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter:CounterUDB:control_7\ \Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter:CounterUDB:count_enable\/main_1 2.314
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_1 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 46.577 MHz 21.470 20.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_183 \Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:count_enable\/main_3 2.331
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_3 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.789
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 46.622 MHz 21.449 20.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.480
Route 1 Net_183 \Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:count_enable\/main_3 2.331
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_3 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.768
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter:CounterUDB:count_stored_i\/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.176 MHz 21.197 20.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(2,3) 1 \Counter:CounterUDB:count_stored_i\ \Counter:CounterUDB:count_stored_i\/clock_0 \Counter:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter:CounterUDB:count_stored_i\ \Counter:CounterUDB:count_stored_i\/q \Counter:CounterUDB:count_enable\/main_2 2.288
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_2 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.789
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
Net_134/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.179 MHz 21.196 20.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,3) 1 Net_134 Net_134/clock_0 Net_134/q 1.250
Route 1 Net_134 Net_134/q \Counter:CounterUDB:count_enable\/main_0 2.287
macrocell4 U(2,3) 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/main_0 \Counter:CounterUDB:count_enable\/q 3.350
Route 1 \Counter:CounterUDB:count_enable\ \Counter:CounterUDB:count_enable\/q \Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.789
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \Counter:CounterUDB:sC16:counterdp:u0\ \Counter:CounterUDB:sC16:counterdp:u0\/clock \Counter:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter:CounterUDB:sC16:counterdp:u0\/co_msb \Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(3,3) 1 \Counter:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:count_stored_i\/main_0 3.331
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 \Sync_1:genblk1[0]:INST\ \Sync_1:genblk1[0]:INST\/clock \Sync_1:genblk1[0]:INST\/out 1.000
Route 1 Net_183 \Sync_1:genblk1[0]:INST\/out \Counter:CounterUDB:count_stored_i\/main_0 2.331
macrocell5 U(2,3) 1 \Counter:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_0\/q \FreqDiv1:count_4\/main_8 4.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,4) 1 \FreqDiv1:count_0\ \FreqDiv1:count_0\/clock_0 \FreqDiv1:count_0\/q 1.250
Route 1 \FreqDiv1:count_0\ \FreqDiv1:count_0\/q \FreqDiv1:count_4\/main_8 3.102
macrocell16 U(2,4) 1 \FreqDiv1:count_4\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_0\/q \FreqDiv1:count_5\/main_8 4.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,4) 1 \FreqDiv1:count_0\ \FreqDiv1:count_0\/clock_0 \FreqDiv1:count_0\/q 1.250
Route 1 \FreqDiv1:count_0\ \FreqDiv1:count_0\/q \FreqDiv1:count_5\/main_8 3.102
macrocell17 U(2,4) 1 \FreqDiv1:count_5\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_5\/q \FreqDiv1:count_6\/main_3 4.361
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,4) 1 \FreqDiv1:count_5\ \FreqDiv1:count_5\/clock_0 \FreqDiv1:count_5\/q 1.250
Route 1 \FreqDiv1:count_5\ \FreqDiv1:count_5\/q \FreqDiv1:count_6\/main_3 3.111
macrocell18 U(2,4) 1 \FreqDiv1:count_6\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_7\/q \FreqDiv1:count_6\/main_1 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,4) 1 \FreqDiv1:count_7\ \FreqDiv1:count_7\/clock_0 \FreqDiv1:count_7\/q 1.250
Route 1 \FreqDiv1:count_7\ \FreqDiv1:count_7\/q \FreqDiv1:count_6\/main_1 3.114
macrocell18 U(2,4) 1 \FreqDiv1:count_6\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_1\/q Net_205/main_8 4.393
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,4) 1 \FreqDiv1:count_1\ \FreqDiv1:count_1\/clock_0 \FreqDiv1:count_1\/q 1.250
Route 1 \FreqDiv1:count_1\ \FreqDiv1:count_1\/q Net_205/main_8 3.143
macrocell2 U(3,4) 1 Net_205 HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_1\/q \FreqDiv1:count_3\/main_2 4.393
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,4) 1 \FreqDiv1:count_1\ \FreqDiv1:count_1\/clock_0 \FreqDiv1:count_1\/q 1.250
Route 1 \FreqDiv1:count_1\ \FreqDiv1:count_1\/q \FreqDiv1:count_3\/main_2 3.143
macrocell15 U(3,4) 1 \FreqDiv1:count_3\ HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_4\/q Net_205/main_5 4.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,4) 1 \FreqDiv1:count_4\ \FreqDiv1:count_4\/clock_0 \FreqDiv1:count_4\/q 1.250
Route 1 \FreqDiv1:count_4\ \FreqDiv1:count_4\/q Net_205/main_5 3.229
macrocell2 U(3,4) 1 Net_205 HOLD 0.000
Clock Skew 0.000
\FreqDiv1:count_4\/q \FreqDiv1:count_6\/main_4 4.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,4) 1 \FreqDiv1:count_4\ \FreqDiv1:count_4\/clock_0 \FreqDiv1:count_4\/q 1.250
Route 1 \FreqDiv1:count_4\ \FreqDiv1:count_4\/q \FreqDiv1:count_6\/main_4 3.235
macrocell18 U(2,4) 1 \FreqDiv1:count_6\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Net_205/q TestSig_1(0)_PAD 23.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,4) 1 Net_205 Net_205/clock_0 Net_205/q 1.250
Route 1 Net_205 Net_205/q TestSig_1(0)/pin_input 6.604
iocell2 P0[7] 1 TestSig_1(0) TestSig_1(0)/pin_input TestSig_1(0)/pad_out 15.495
Route 1 TestSig_1(0)_PAD TestSig_1(0)/pad_out TestSig_1(0)_PAD 0.000
Clock Clock path delay 0.000