Static Timing Analysis

Project : test
Build Time : 10/20/13 14:14:27
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
stepper_1_Clock_1 CyHFCLK 10.000 kHz 10.000 kHz 39.179 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 39.179 MHz 25.524 99974.476
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \stepper_1:Counter:CounterUDB:control_7\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:count_enable\/main_0 2.246
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_0 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 41.334 MHz 24.193 99975.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/clock_0 \stepper_1:Counter:CounterUDB:count_stored_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_2 2.245
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_2 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 41.355 MHz 24.181 99975.819
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/clock_0 \stepper_1:Counter:CounterUDB:disable_run_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_1 2.233
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_1 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\stepper_1:Net_336\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 41.358 MHz 24.179 99975.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \stepper_1:Net_336\ \stepper_1:Net_336\/clock_0 \stepper_1:Net_336\/q 1.250
Route 1 \stepper_1:Net_336\ \stepper_1:Net_336\/q \stepper_1:Counter:CounterUDB:count_enable\/main_3 2.231
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_3 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 44.956 MHz 22.244 99977.756
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \stepper_1:Counter:CounterUDB:control_7\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:count_enable\/main_0 2.246
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_0 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 44.958 MHz 22.243 99977.757
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \stepper_1:Counter:CounterUDB:control_7\ \stepper_1:Counter:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \stepper_1:Counter:CounterUDB:count_enable\/main_0 2.246
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_0 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.547
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 47.817 MHz 20.913 99979.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/clock_0 \stepper_1:Counter:CounterUDB:count_stored_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_2 2.245
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_2 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.819 MHz 20.912 99979.088
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/clock_0 \stepper_1:Counter:CounterUDB:count_stored_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:count_stored_i\ \stepper_1:Counter:CounterUDB:count_stored_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_2 2.245
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_2 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.547
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 47.845 MHz 20.901 99979.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/clock_0 \stepper_1:Counter:CounterUDB:disable_run_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_1 2.233
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_1 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.548
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.847 MHz 20.900 99979.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/clock_0 \stepper_1:Counter:CounterUDB:disable_run_i\/q 1.250
Route 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:count_enable\/main_1 2.233
macrocell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/main_1 \stepper_1:Counter:CounterUDB:count_enable\/q 3.350
Route 1 \stepper_1:Counter:CounterUDB:count_enable\ \stepper_1:Counter:CounterUDB:count_enable\/q \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.547
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/clock \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \stepper_1:Counter:CounterUDB:sC16:counterdp:u0\/co_msb \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \stepper_1:Counter:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\stepper_1:Net_336\/q \stepper_1:Counter:CounterUDB:count_stored_i\/main_0 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \stepper_1:Net_336\ \stepper_1:Net_336\/clock_0 \stepper_1:Net_336\/q 1.250
Route 1 \stepper_1:Net_336\ \stepper_1:Net_336\/q \stepper_1:Counter:CounterUDB:count_stored_i\/main_0 2.231
macrocell2 U(1,0) 1 \stepper_1:Counter:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
\stepper_1:Net_336\/q \stepper_1:Net_336\/main_0 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \stepper_1:Net_336\ \stepper_1:Net_336\/clock_0 \stepper_1:Net_336\/q 1.250
macrocell13 U(1,0) 1 \stepper_1:Net_336\ \stepper_1:Net_336\/q \stepper_1:Net_336\/main_0 2.231
macrocell13 U(1,0) 1 \stepper_1:Net_336\ HOLD 0.000
Clock Skew 0.000
\stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:disable_run_i\/main_1 3.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/clock_0 \stepper_1:Counter:CounterUDB:disable_run_i\/q 1.250
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ \stepper_1:Counter:CounterUDB:disable_run_i\/q \stepper_1:Counter:CounterUDB:disable_run_i\/main_1 2.233
macrocell3 U(1,0) 1 \stepper_1:Counter:CounterUDB:disable_run_i\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_0\/q \stepper_1:Net_336\/main_5 3.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/clock_0 \stepper_1:FreqDiv:count_0\/q 1.250
Route 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/q \stepper_1:Net_336\/main_5 2.518
macrocell13 U(1,0) 1 \stepper_1:Net_336\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_1\/main_4 3.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/clock_0 \stepper_1:FreqDiv:count_0\/q 1.250
Route 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_1\/main_4 2.521
macrocell9 U(1,0) 1 \stepper_1:FreqDiv:count_1\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_2\/main_2 3.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/clock_0 \stepper_1:FreqDiv:count_0\/q 1.250
Route 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_2\/main_2 2.521
macrocell10 U(1,0) 1 \stepper_1:FreqDiv:count_2\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_3\/main_4 3.771
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/clock_0 \stepper_1:FreqDiv:count_0\/q 1.250
Route 1 \stepper_1:FreqDiv:count_0\ \stepper_1:FreqDiv:count_0\/q \stepper_1:FreqDiv:count_3\/main_4 2.521
macrocell11 U(1,0) 1 \stepper_1:FreqDiv:count_3\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_1\/q \stepper_1:Net_336\/main_4 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \stepper_1:FreqDiv:count_1\ \stepper_1:FreqDiv:count_1\/clock_0 \stepper_1:FreqDiv:count_1\/q 1.250
Route 1 \stepper_1:FreqDiv:count_1\ \stepper_1:FreqDiv:count_1\/q \stepper_1:Net_336\/main_4 2.522
macrocell13 U(1,0) 1 \stepper_1:Net_336\ HOLD 0.000
Clock Skew 0.000
\stepper_1:FreqDiv:count_1\/q \stepper_1:FreqDiv:count_1\/main_3 3.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \stepper_1:FreqDiv:count_1\ \stepper_1:FreqDiv:count_1\/clock_0 \stepper_1:FreqDiv:count_1\/q 1.250
macrocell9 U(1,0) 1 \stepper_1:FreqDiv:count_1\ \stepper_1:FreqDiv:count_1\/q \stepper_1:FreqDiv:count_1\/main_3 2.526
macrocell9 U(1,0) 1 \stepper_1:FreqDiv:count_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyHFCLK
Source Destination Delay (ns)
\stepper_1:outputs:Sync:ctrl_reg\/control_3 Pin_1(0)_PAD 24.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,1) 1 \stepper_1:outputs:Sync:ctrl_reg\ \stepper_1:outputs:Sync:ctrl_reg\/busclk \stepper_1:outputs:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_4 \stepper_1:outputs:Sync:ctrl_reg\/control_3 Pin_1(0)/pin_input 5.590
iocell1 P0[1] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.980
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
\stepper_1:outputs:Sync:ctrl_reg\/control_4 Pin_2(0)_PAD 24.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,1) 1 \stepper_1:outputs:Sync:ctrl_reg\ \stepper_1:outputs:Sync:ctrl_reg\/busclk \stepper_1:outputs:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_5 \stepper_1:outputs:Sync:ctrl_reg\/control_4 Pin_2(0)/pin_input 5.968
iocell2 P0[0] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.530
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\stepper_1:resetCounter:Sync:ctrl_reg\/control_0 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\/reset 170.184 MHz 5.876 99994.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \stepper_1:resetCounter:Sync:ctrl_reg\ \stepper_1:resetCounter:Sync:ctrl_reg\/clock \stepper_1:resetCounter:Sync:ctrl_reg\/control_0 2.580
Route 1 \stepper_1:Net_326\ \stepper_1:resetCounter:Sync:ctrl_reg\/control_0 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\/reset 3.296
statusicell1 U(0,0) 1 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\stepper_1:resetCounter:Sync:ctrl_reg\/control_0 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\/reset 5.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \stepper_1:resetCounter:Sync:ctrl_reg\ \stepper_1:resetCounter:Sync:ctrl_reg\/clock \stepper_1:resetCounter:Sync:ctrl_reg\/control_0 2.040
Route 1 \stepper_1:Net_326\ \stepper_1:resetCounter:Sync:ctrl_reg\/control_0 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\/reset 3.296
statusicell1 U(0,0) 1 \stepper_1:Counter:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000