Static Timing Analysis

Project : read_speed_test
Build Time : 05/17/17 15:22:53
Device : CY8C4248BZI-L489
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 3.30
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_intClock(FFB) ADC_intClock(FFB) 1.143 MHz 1.143 MHz N/A
Clock_1(FFB) Clock_1(FFB) 12.000 MHz 12.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
Clock_1 CyHFCLK 12.000 MHz 12.000 MHz N/A
Clock_3 CyHFCLK 2.000 MHz 2.000 MHz 39.194 MHz
ADC_intClock CyHFCLK 1.143 MHz 1.143 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 39.194 MHz 25.514 474.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \Counter_Spd:CounterUDB:control_7\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:count_enable\/main_0 2.237
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_0 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.547
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 41.358 MHz 24.179 475.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/clock_0 \Counter_Spd:CounterUDB:prevCapture\/q 1.250
Route 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:count_enable\/main_1 2.232
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_1 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.547
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Skew 0.000
\Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 44.976 MHz 22.234 477.766
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \Counter_Spd:CounterUDB:control_7\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:count_enable\/main_0 2.237
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_0 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.547
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/cs_addr_1 44.978 MHz 22.233 477.767
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,0) 1 \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/clock \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 2.580
Route 1 \Counter_Spd:CounterUDB:control_7\ \Counter_Spd:CounterUDB:sCTRLReg:ctrlreg\/control_7 \Counter_Spd:CounterUDB:count_enable\/main_0 2.237
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_0 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.546
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 47.849 MHz 20.899 479.101
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/clock_0 \Counter_Spd:CounterUDB:prevCapture\/q 1.250
Route 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:count_enable\/main_1 2.232
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_1 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.547
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:sC16:counterdp:u1\/cs_addr_1 47.851 MHz 20.898 479.102
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/clock_0 \Counter_Spd:CounterUDB:prevCapture\/q 1.250
Route 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:count_enable\/main_1 2.232
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_1 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u1\/cs_addr_1 2.546
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ SETUP 11.520
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 62.838 MHz 15.914 484.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 3.540
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.ce0__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0i 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0i \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_Spd:CounterUDB:per_equal\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:status_2\/main_0 2.237
macrocell3 U(0,0) 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/main_0 \Counter_Spd:CounterUDB:status_2\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 2.257
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_0 63.008 MHz 15.871 484.129
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 3.510
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.ce1__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1i 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1i \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb 2.950
Route 1 \Counter_Spd:CounterUDB:cmp_out_i\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb \Counter_Spd:CounterUDB:status_0\/main_0 2.240
macrocell2 U(0,0) 1 \Counter_Spd:CounterUDB:status_0\ \Counter_Spd:CounterUDB:status_0\/main_0 \Counter_Spd:CounterUDB:status_0\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_0\ \Counter_Spd:CounterUDB:status_0\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_0 2.251
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_4 67.737 MHz 14.763 485.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,0) 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/clock_0 \Counter_Spd:CounterUDB:prevCapture\/q 1.250
Route 1 \Counter_Spd:CounterUDB:prevCapture\ \Counter_Spd:CounterUDB:prevCapture\/q \Counter_Spd:CounterUDB:hwCapture\/main_0 2.232
macrocell1 U(0,0) 1 \Counter_Spd:CounterUDB:hwCapture\ \Counter_Spd:CounterUDB:hwCapture\/main_0 \Counter_Spd:CounterUDB:hwCapture\/q 3.350
Route 1 \Counter_Spd:CounterUDB:hwCapture\ \Counter_Spd:CounterUDB:hwCapture\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_4 6.361
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 69.089 MHz 14.474 485.526
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb 5.060
Route 1 \Counter_Spd:CounterUDB:per_equal\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:status_2\/main_0 2.237
macrocell3 U(0,0) 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/main_0 \Counter_Spd:CounterUDB:status_2\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 2.257
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb 3.210
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:overflow_reg_i\/main_0 5.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_Spd:CounterUDB:per_equal\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:overflow_reg_i\/main_0 2.237
macrocell7 U(0,0) 1 \Counter_Spd:CounterUDB:overflow_reg_i\ HOLD 0.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb \Counter_Spd:CounterUDB:prevCompare\/main_0 5.330
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb 3.090
Route 1 \Counter_Spd:CounterUDB:cmp_out_i\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb \Counter_Spd:CounterUDB:prevCompare\/main_0 2.240
macrocell8 U(0,0) 1 \Counter_Spd:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_Spd:CounterUDB:overflow_reg_i\/main_0 6.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 1.900
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.ce0__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce0 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0i 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0i \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.270
Route 1 \Counter_Spd:CounterUDB:per_equal\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:overflow_reg_i\/main_0 2.237
macrocell7 U(0,0) 1 \Counter_Spd:CounterUDB:overflow_reg_i\ HOLD 0.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 \Counter_Spd:CounterUDB:prevCompare\/main_0 6.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 2.030
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.ce1__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/ce1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1i 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1i \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb 2.270
Route 1 \Counter_Spd:CounterUDB:cmp_out_i\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce1_comb \Counter_Spd:CounterUDB:prevCompare\/main_0 2.240
macrocell8 U(0,0) 1 \Counter_Spd:CounterUDB:prevCompare\ HOLD 0.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0_comb \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_1 6.629
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0_comb 3.270
Route 1 \Counter_Spd:CounterUDB:status_1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0_comb \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_1 5.359
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:prevCompare\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_0 7.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,0) 1 \Counter_Spd:CounterUDB:prevCompare\ \Counter_Spd:CounterUDB:prevCompare\/clock_0 \Counter_Spd:CounterUDB:prevCompare\/q 1.250
Route 1 \Counter_Spd:CounterUDB:prevCompare\ \Counter_Spd:CounterUDB:prevCompare\/q \Counter_Spd:CounterUDB:status_0\/main_1 2.241
macrocell2 U(0,0) 1 \Counter_Spd:CounterUDB:status_0\ \Counter_Spd:CounterUDB:status_0\/main_1 \Counter_Spd:CounterUDB:status_0\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_0\ \Counter_Spd:CounterUDB:status_0\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_0 2.251
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u0\/z0 \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_1 7.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u0\/z0 1.740
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.z0__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/z0 \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0i \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0_comb 2.740
Route 1 \Counter_Spd:CounterUDB:status_1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/z0_comb \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_1 5.359
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:overflow_reg_i\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 8.268
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,0) 1 \Counter_Spd:CounterUDB:overflow_reg_i\ \Counter_Spd:CounterUDB:overflow_reg_i\/clock_0 \Counter_Spd:CounterUDB:overflow_reg_i\/q 1.250
Route 1 \Counter_Spd:CounterUDB:overflow_reg_i\ \Counter_Spd:CounterUDB:overflow_reg_i\/q \Counter_Spd:CounterUDB:status_2\/main_1 3.411
macrocell3 U(0,0) 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/main_1 \Counter_Spd:CounterUDB:status_2\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 2.257
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 8.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/clock \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb 2.960
Route 1 \Counter_Spd:CounterUDB:per_equal\ \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ce0_comb \Counter_Spd:CounterUDB:status_2\/main_0 2.237
macrocell3 U(0,0) 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/main_0 \Counter_Spd:CounterUDB:status_2\/q 3.350
Route 1 \Counter_Spd:CounterUDB:status_2\ \Counter_Spd:CounterUDB:status_2\/q \Counter_Spd:CounterUDB:sSTSReg:stsreg\/status_2 2.257
statusicell1 U(0,0) 1 \Counter_Spd:CounterUDB:sSTSReg:stsreg\ HOLD -2.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_3
Source Destination Delay (ns)
Pin_1(0)_PAD \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 34.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_1(0)_PAD Pin_1(0)_PAD Pin_1(0)/pad_in 0.000
iocell8 P3[0] 1 Pin_1(0) Pin_1(0)/pad_in Pin_1(0)/fb 9.097
Route 1 Net_1490 Pin_1(0)/fb \Counter_Spd:CounterUDB:count_enable\/main_2 4.597
macrocell4 U(0,0) 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/main_2 \Counter_Spd:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_Spd:CounterUDB:count_enable\ \Counter_Spd:CounterUDB:count_enable\/q \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 2.547
datapathcell1 U(1,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb 9.710
Route 1 \Counter_Spd:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \Counter_Spd:CounterUDB:sC16:counterdp:u0\/co_msb \Counter_Spd:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \Counter_Spd:CounterUDB:sC16:counterdp:u1\ SETUP 5.090
Clock Clock path delay 0.000