what's the DMA transfer block size of the XMC4400 ?!

[Tim_Shih]

Dear Receiver,

In the following link,

https://www.infineon.com/dgdl/Infineon-GPDMA-XMC4000-AP32290-AN-v01_00-EN.pdf?fileId=5546d4624e765da...

Chapter 3: DMA transfer block size,

I would like to know the  what's the size of "DMA transfer block"?!

Because I can find this information in the AP32290 app note.

Thank you so much.

[LinglingG_46]

1: DMA transfer block size is defined by yourself. The value range is from 0-4095.

2: One block size width is 8bit,16bit or 32bit.

For example:

[Tim_Shih]

ok ok, 

One more question, why there're no "0-4095" range description is written in the AP32290 app note?

Does this "0-4095" range depend on MCU hardware design?! 

Thank you so much. 

[LinglingG_46]

1：

The GPDMA0 channels 0 and 1 provide a FIFO of 32 Bytes (eight 32-bit entries). These
channels can be used to execute burst transfers up to a fixed length burst size of 8. The
remaining channels FIFO size is 8 Bytes.

2：At the same time, the DMA source and destination data restricted by the register. BLOCK_TS is 0-11bits, which max value is 4095.

[michael_liao]

Hi Lingling,

1. Is the range from 0-4095 depends on MCU?

If it is, what's the range of XMC4700?

2. Why the block size is limited by this range?

[LinglingG_46]

Yes, it is the same on the XMC4700. we can read the register.

[michael_liao]

Hi @LinglingG_46 ,

I am not sure about the BLOCK_TS means.

If the block size 256, then the BLOCK_TS should be set to 255 or 256?

If the block size 4096, then the BLOCK_TS should be set to 4095 or 4096?

Would  BLOCK_TS  overflow?

[LinglingG_46 · Accepted solution]

Hi,

Please check the XMC4400 reference manual: https://www.infineon.com/dgdl/Infineon-xmc4400_rm_v1.6_2016-UM-v01_06-EN.pdf?fileId=db3a30433afc7e3e...

The register which to config the block size is 11 bits, so the max value is 2^12-1=4095.