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ziad-shaarawy
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I'm utilizing Dave apps to set up the XMC1400 as an SPI master. Can I modify the clock settings from receive on rising edge to receive on t falling edge once the code has been generated?

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Pradeep_PN
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50 likes received 250 sign-ins 100 solutions authored

Hi @ziad-shaarawy ,

It is possible to change t the shift clock output signal SCLKOUT with respect to SCLK. This is done in the block SCLKCFG (shift clock configuration) by bit field BRG.SCLKCFG, allowing 4 possible settings.

Based on your requirement use the API  " XMC_SPI_CH_ConfigureShiftClockOutput() " 

The description of above API is : Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.

In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available for external slave devices by SCLKOUT signal.
In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.
The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock period. These settings are applicable only in master mode.

Base on your requirements please use that.

Best Regards
Pradeep.

 

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Pradeep_PN
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 100 solutions authored

Hi @ziad-shaarawy ,

It is possible to change t the shift clock output signal SCLKOUT with respect to SCLK. This is done in the block SCLKCFG (shift clock configuration) by bit field BRG.SCLKCFG, allowing 4 possible settings.

Based on your requirement use the API  " XMC_SPI_CH_ConfigureShiftClockOutput() " 

The description of above API is : Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.

In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available for external slave devices by SCLKOUT signal.
In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.
The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock period. These settings are applicable only in master mode.

Base on your requirements please use that.

Best Regards
Pradeep.

 

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