XMC™ Forum Discussions
Hi Infineon Team,
We are interested to purchase 2.0kW EV charger (EVAL_2KW_48V_CHAR_P7) and 3kW (EVAL_3KW_50V_PSU).
Just want to clarify, upon purchase will the complete SW source code in C will be provided or only the (.exe ) executable file will be given.
Best Regards
Milan
Zepco Technologies
Show LessHello,
I just wanted to share some experience I had with XMC4500 and XMC4700.
I ran into an issue in the past here (don't go to look at it ("XMC-in-lock-up-scenario..."), as it is now fully deprecated), and thought I was experimenting SSW issue (boot software). Now I have found exactly what was happening last week. I was doing some measurements that had me look at the level of an XMC input pin with a 10k pull-up resistor to 3.3V, while recording internal values in the XMC RAM, that allowed my to see that I was mistaking (ie there was no lock-up at all), and it provided me an easy method for reproducing the issue (which I kind of lacked back in the days) in a way I could do measurements in all safety (that was very slightly unsafe back in the days).
We have a dedicated board that work in a hostile environnement, and there is XMC4X00 on it, as well as an external watchdog. We protected it really well but we still have some rares issues with it in the field. We have leds on it. When the issue happen, they all lit (this is what did make me think my board was stuck in some kind of 3state init of the XMC, but it is not).
In our labo, we can reproduce the issue using a bursts generator with the setting 5.5kV 5kHz 5ms. We then apply this with a 1pF coupling on a random GPIO pin of the XMC. We did protect the pins with 1nF capacitors, so due to the coupling, the XMC pin get a very limited perturbation current.
What is happening is that during the bursts, the PORST peripheral is hardwarely disturbed. One would assume the level read on the GPIOs would be random like 1, 0, 0 ,1 ,0, 1 etc, but in fact someting else is happening.
The issue can either be transient or permanent. What it does, is that all ports that have an output driver are set as output low (I didn't check every pin, but all the ones I have accessible in P1,2,3,4,5 were). When that happen, I can read the registers of the PORTS, and everything is set as during my init. So the content of the PORST registers do not correspond to the behaviour of the pins.
Notice that the pins set as inputs, are also forced to 0V by hardware. I've tried a few things, like making sure there is no hibernation, that the hardware control was disabled, and even tried to initialise the OUT register to high for my inputs (thinking it may short it to high level then, but it didn't), but nothing helped.
The only workaround known is to reset the PORTS peripheral. As soon as it is in reset, the pin go from hardwarly forced low to 3state. If programmed again, everything works as expected.
For my project, it is quite annoying. The good thing is that the PORTS slices IN registers content are still working as expected. So I can detect when the issue occur as I then read all my inputs are low level (that can never occur in another normal situation). If that occur during 1ms consecutively, I issue a global SWReset.
By chance, my PWM are active low, but the enable gating is active high. I have an external watchdog as well. And the XMC can reset it by putting a pin low. So when the lock-up of the PORTS peripheral occur, my system is put in a safe state automatically.
One interesting thing to note, is that the PORT 14 and 15 which have no output drivers are not affected. So my ADC still give me the correct values. Even better, I had put some important digital inputs on P14-15. Those are working perfectly, and it help me figuring out if I should perform a SWReset or not.
So my system can run fine in a safestate, with just PORT 1,2,3,4,5 forced to level. All the rest of my peripherals are running correctly. The timers do the correct timings, the interrupts are working, the code does what is programmed to do etc. It is only an I/O issue. Obviously, it is not really a good surprise to have my inputs forced to 0V, especially because my inputs are something else outputs, so it shorts. In practise, the shorts seems not to be very problematic for me, since everything is internaly current limited.
I think the PORST issue should be added to the errata by the way. Even with workaround: PORTS reset.
A simple external pull-up on an XMC input can be sufficient for detection and workaround. Maybe it can even works with an internal weak pull-up.
Here is an example of measurements:
I have an external 100us clock in blue (actually not connected to the XMC and vary between +1V and +2V). The pink signal is an input of the XMC that is connected to an external 10k pull-up to the +3.3V. This pin is initialised as an input in the XMC, and the +3.3V supply is not disturbed at all.
When the bursts occur (5ms of 5kHz pulses, we can see the noise added on the blue signal), we can see the pin gets pulled low by the XMC. This can be transient, or permanent like on the last image. Note that a permanent problem can occur, even if only one pulses is given. It doesn't have to occur at the end.
PS: To determine what was the problem, I did record the inputs pin levels, and PORTS registers, as other key variables content into the RAM. By connecting the debugger to the running target with a breakpoint placed on the very first instruction in startup.c, it reset the registers and halt the XMC. The RAM content stay untouched, which allowed me to record 1s before and 1s after the bursts application, at a 100us sampling interval, binary dump the RAM zone with gdb, and import in within a python script for browsing the data. The input levels were exactly matching what I could record with my oscilloscope.
On the following python graph, we can see the pink trace from my scope that correspond exactly to the orange trace at the end of the arrow, which is the XMC "100us sampling" of the externally pulled-up input (pink trace).
Best regards,
Relafe
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when I go to properties it only provides me this option How to do optimisation or custom library addition in the properties under c/c++ built setting
Show LessI am using XMC4108 controller for testing CAN communication. I configured CAN for 1mbps speed. i am testing transmission and reception with PCAN . Transmission is working fine.
CAN_NODE_MO_Receive(HandlePtr1->lmobj_ptr[0]) with this API i am trying to receive the CAN data from the PCAN but not able to receive with this API .
Please give some suggestions to resolve this issue.
Regards,
Ranjitha
Show LessHey folks,
I am working with XMC4400 platform2go and trying to have command line interaction with it from Windows machine.
After checking the community, I think below the 2 posts are quite related to what I want to do.
https://community.infineon.com/t5/XMC/XMC4400-Platform2Go-UART-Communication-with-PC/td-p/388671
https://community.infineon.com/t5/XMC/Not-showing-VCOM-USB-port/td-p/303725
So, I followed what suggested in the posts above, downloaded USBD_VCOM_APP_Example_XMC45 example and try to build it locally and test it.
I went through the steps of installing the USV VCOM driver, with Device Manager -> Add legacy hardware -> install...manually ... ->Show All Devices -> HaveDisk -> Install From disck, and located the driver at the USBD_VCOM_APP_Example_XMC45 project folder Dave/Generated/USBD_VCOM/inf/
After that, following the readme in the USBD_VCOM_APP_Example_XMC45 project, which shows
The communications port did appear in my device manager, but with a "!" symbol.
And I tried to putty to it,
which gives me
Is there some advice on this?
btw my system is windows 11.
Thanks in advance.
Regards,
Wei
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Hello,
As I have mentioned before, I am trying to create an abstraction layer for the CAN bus in C++ on an XMC700 family device.
I want to use this application in an RTOS and in other device families I am used to creating an RTOS thread for querying the hardware CAN receive buffers and putting them onto an RTOS queue.
The challenge I have is that the only CAN receive examples use an interrupt-driven call back which requires a globally scoped named function. This is very challenging as I can link directly to a class function's name without declaring that function as static and eliminating a lot of the benefit of the code reuse across the different CAN bus devices on the chip.
Is there a way or examples of how I can write a function to check the receive buffer of the CAN hw and extract any new messages in a polling fashion that would align better with the RTOS?
Show LessHi all,
we are using XMC4800E196K2048 in our electronic design. According to reference manual (V1.3, 2016-07 | ECAT v1.1) the ethercat module of the chip provides functionality of link detection over MII management interface. There is the register MII Management Control/Status (0x54010510) which contains MI Link Detection bit. The bit is set to zero, meaning link detection is not available. In the description field to the bit-field registers 0x0516-0x0517 are referenced (Register MII Management ECAT Access State and PDI Access State).
Here is ethercat config we are using:XMC_ECAT_CONFIG_t ecatConfig = {.dword = { 0x00810280, 0x00000000, 0x00000000, 0x00D10000}};
Here is ethercat port control config we are using:
XMC_ECAT_PORT_CTRL_t ports = {
.common =
{
.enable_rstreq = false,
.latch_input0 = XMC_ECAT_PORT_CTRL_LATCHIN0_P14_5,
.latch_input1 = XMC_ECAT_PORT_CTRL_LATCHIN1_P14_4,
.phyaddr_offset = 0x3,
.mdio = XMC_ECAT_PORT_CTRL_MDIO_P0_12,
},
.port0 =
{
.rxd0 = XMC_ECAT_PORT0_CTRL_RXD0_P5_0,
.rxd1 = XMC_ECAT_PORT0_CTRL_RXD1_P5_1,
.rxd2 = XMC_ECAT_PORT0_CTRL_RXD2_P5_2,
.rxd3 = XMC_ECAT_PORT0_CTRL_RXD3_P5_7,
.rx_clk = XMC_ECAT_PORT0_CTRL_RX_CLK_P1_1,
.rx_dv = XMC_ECAT_PORT0_CTRL_RX_DV_P1_9,
.rx_err = XMC_ECAT_PORT0_CTRL_RX_ERR_P4_0,
.link = XMC_ECAT_PORT1_CTRL_LINK_GND,
.tx_clk = XMC_ECAT_PORT0_CTRL_TX_CLK_P9_1,
.tx_shift = XMC_ECAT_PORT0_CTRL_TX_SHIFT_0NS,
},
.port1 =
{
.rxd0 = XMC_ECAT_PORT1_CTRL_RXD0_P8_4,
.rxd1 = XMC_ECAT_PORT1_CTRL_RXD1_P0_6,
.rxd2 = XMC_ECAT_PORT1_CTRL_RXD2_P0_5,
.rxd3 = XMC_ECAT_PORT1_CTRL_RXD3_P0_4,
.rx_clk = XMC_ECAT_PORT1_CTRL_RX_CLK_P0_1,
.rx_dv = XMC_ECAT_PORT1_CTRL_RX_DV_P0_9,
.rx_err = XMC_ECAT_PORT1_CTRL_RX_ERR_P15_2,
.link = XMC_ECAT_PORT1_CTRL_LINK_GND,
.tx_clk = XMC_ECAT_PORT1_CTRL_TX_CLK_P0_10,
.tx_shift = XMC_ECAT_PORT1_CTRL_TX_SHIFT_0NS,
},
};
The PHY on port 1 has PHY address 4.
The Enhanced Link Detection MII bit is set in the ECAT0_FEATURE register.
The Enhanced Link Detection bit is set in the ECAT0_ESC_DL_STATUS register.
The Enhanced Link detection all ports bit is set in the ECAT0_ESC_CONFIG register.
I would assume that the ecat module periodically reads out the status register of the phy, but there is no activity on the MII line that goes to the chip.
I changed ethercat config and set enable_enhanced_link_p0 and enable_enhanced_link_p1 bits, but this also did not help. When setting those bits I set checksum field to 0x88A4, as advised here: https://download.beckhoff.com/download/document/io/ethercat-development-products/ethercat_esc_datasheet_sec1_technology_2i3.pdf (page 78).
Many thanks.
Best Regards,
Mykola
Show LessHi, I have a question about DC-Link Capacitor for PMSM, How to calculate the volume of the DC-Link Capacitor for PMSM? For example the DC-Link Voltage is 85V, the MAX current of PMSM is 300A, the delta Voltage is 2.5%*85V,the switching frequency is 10KHZ.
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