XMC™ Forum Discussions
XMC™
Hi all, Am new to infineon XMC4400 series...could anyone please suggest me what are the best tools(IDE,compiler, debugger, RTOS etc) for XMC4400 f64k2...
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Hi all,
Am new to infineon XMC4400 series...could anyone please suggest me what are the best tools(IDE,compiler, debugger, RTOS etc) for XMC4400 f64k256.
Thanks,
shweta Show Less
Am new to infineon XMC4400 series...could anyone please suggest me what are the best tools(IDE,compiler, debugger, RTOS etc) for XMC4400 f64k256.
Thanks,
shweta Show Less
XMC™
Hello,I set up a SPI connection on the XMC4300 using the USIC0_CH1 with the following pins :CS (SELO0) : P2.3, SCLK (SCLKOUT) : P2.4, MISO (DX0A) : P2...
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Hello,
I set up a SPI connection on the XMC4300 using the USIC0_CH1 with the following pins :
CS (SELO0) : P2.3, SCLK (SCLKOUT) : P2.4, MISO (DX0A) : P2.2, MOSI (DOUT0) : P2.5.
For testing, I changed with success P2.3 with pin P1.14 (SELO2).
However, when I want to use another pins configuration, with USIC0_CH0, with the following pins:
CS (SELO0): P0.7, SCLK (SCLKOUT) : P0.8, MISO (DX0D) : P5.0, MOSI (DOUT0) : P1.5,
It doesn’t work.
Any ideas why ?
The register configuration are the same, except for the pins and for the input control register (DXOCR.DSEL)
Here my configuration :
Thank you in advance,
Nicolas Show Less
I set up a SPI connection on the XMC4300 using the USIC0_CH1 with the following pins :
CS (SELO0) : P2.3, SCLK (SCLKOUT) : P2.4, MISO (DX0A) : P2.2, MOSI (DOUT0) : P2.5.
For testing, I changed with success P2.3 with pin P1.14 (SELO2).
However, when I want to use another pins configuration, with USIC0_CH0, with the following pins:
CS (SELO0): P0.7, SCLK (SCLKOUT) : P0.8, MISO (DX0D) : P5.0, MOSI (DOUT0) : P1.5,
It doesn’t work.
Any ideas why ?
The register configuration are the same, except for the pins and for the input control register (DXOCR.DSEL)
Here my configuration :
/* Release reset of USIC module by writing a 1 to the USICxRS bit in SCU_PRCLR0 or SCU_PRCLR1 registers */
SCU_RESET->PRCLR0 |= (1<<11);
// ------------------------------------------------------------
// 1.Enable USICx channel n
// ------------------------------------------------------------
// Mode Control RM 18.2.2.2, Kernel State Configuration Register RM 18.11.3.3 :
// BPMODEN MODEN
SPI_CH->KSCFG |= (1 << 1)| (1 << 0);
// Run mode 0 : Channel operation as specified, no impact on data transfer
// Channel Control Register RM 18.11.3.1
// Select SSC Mode for USIC Channel 0 : put at 0 for configuration
//SPI_CH->CCR &= (0 << 3)| (0 << 2)| (0 << 1)| (0 << 0);
// ------------------------------------------------------------
// ------------------------------------------------------------
// 2.Configure Baud Rate Generator Register (BRG) RM 18.11.6.2
// - Normal divider mode
// - Baud rate = SCLK
// - PDIV (Divider factor) = 71 -> SCLK = 1 Mbit/s / PDIV = 5 -> SCLK = 12 Mbit/s / PDIV = 8 -> SCLK = 8 Mbit/s
// - Delay : Tld = 10 us with CTQSEL = 2 and DCTQ = 10 for SCLK = 1 Mbit/s
// - Delay : Tld = 10.3 us with CTQSEL = 2, DCTQ = 31 and PCTQ = 3 for SCLK = 12 Mbit/s
// - Delay : Tld = 1 us with CTQSEL = 2, DCTQ = 1 and PCTQ = 7 for SCLK = 8 Mbit/s
// - Delay : Tld = 6 us with CTQSEL = 2, DCTQ = 6 and PCTQ = 7 for SCLK = 8 Mbit/s
// - Delay : Tld = 8 us with CTQSEL = 2, DCTQ = 8 and PCTQ = 7 for SCLK = 8 Mbit/s
// - SCLKCFG = 00b, cf RM 18.4.1.2 Shift Clock Signals : data transmitted on the rising edge of the clock and the data received on the falling edge of the clock (CPOL = 0, CPHA = 0)
// - SCLKOSEL = 0b : SCLK from the baud rate generator is selected as the SCLKOUT input source.
// - CLKSEL = 00b : the fractional divider frequency Ffd is selected
// - PPPEN = 0b : This bit defines the input frequency fPPP. PPPEN = 0b : The 2:1 divider for fPPP is disabled, fPPP = fPIN = 144 mhz .
// ------------------------------------------------------------
// DM = 0b01 STEP = 1023 = 0x3FF = 0b001111111111
SPI_CH->FDR = (1 << 14) | ( 1023 << 0);
// PDIV DCTQ CTQSEL PCTQ SCLKCFG
SPI_CH->BRG = (8 << 16) | (1 << 10) | (2 << 6) | (3<<8) ; //| (2 << 30)
// ------------------------------------------------------------
// ------------------------------------------------------------
// 3.Configure input stages : Input Control Registers RM 17.11.5.1
// - Select input DX0A -> DSEL = 0b000, input DX0D -> DSEL = 0b011
// - Derive input of data shift unit directly from input pin
// - DSEN = 1 : The synchronized signal can be taken as input for the data shift unit.
// cf RM 18.11.5.1 Input Control Registers and RM 18.4.3 Operating the SSC in Master Mode
// - INSW = 1 : The input of the data shift unit is connected to the selected data input line. This setting is used
// if the signals are directly derived from an input pin without treatment by the protocol preprocessor
// ------------------------------------------------------------
// DSEN INSW DSEL
SPI_CH->DX0CR = (1 << 6) | (1 << 4) | (0b011 << 0);
// ------------------------------------------------------------
// ------------------------------------------------------------
// 4.Configure data format : SCTR Shift Control Register RM 18.11.7.1
// - Data word = 16 bits
// - FLE = 63 : the lengh of the frame is not set, and external fctors can end the transmision, not based on frame length
// - PDL = 0 : This bit defines the output level at the shift data output signal when no data is available for transmission. passive level is 0
// - SDIR = 1 : MSB first
// - TRM = 01b :The shift control signal is considered active if it is at 1-level. This is the setting to be
// programmed to allow data transfers.
// - DSM = 00b : Data Shift Mode : Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0
// ------------------------------------------------------------
// WLE = 0xF FLE (63 = infinite) TRM SDIR
SPI_CH->SCTR = ( 15<<24 ) | ( 63<<16 ) | ( 1<<8 ) | ( 1<<0 );
// ------------------------------------------------------------
// ------------------------------------------------------------
// 5.Configure data transfer parameters : TCSR Transmission Control and Status Register RM 18.11.7.2
// - Single shot transmission of data word when a valid word is available
// - WLEMD = 0b : WLE Mode means the TCSR.EOF (End Of Frame) bit is not automatically changed.
// - SELMD = 0b : we have only one slave: Select Mode : automatically update bit field PCR.CTR[20:16] by the transmit control information TCI[4:0] and clear bit field
// - PCR.CTR[23:21] (see Page 18-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the
// transmit buffer input locations TBUFx or by an optional data buffer.
// - WLE Mode : This bit enables the data handler to automatically update the bit field SCTR.WLE by the transmit control information TCI[3:0] and bit TCSR.EOF by TCI[4]
// (see Page 18-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer
// input locations TBUFx or by an optional data buffer.
// - SOF = 1b : Start of Frame : The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated
// (respecting the programmed delays).
// So after have sending a frame, the PCR.MSLSEN (slave select) is automatically deactivated.
// So the Slave Select is deactivated after send 8 bits.
// - EOF : End of Frame : If it is the last word, the MSLS signal becomes inactive after the transfer, respecting the programmed delays. This bit becomes
// cleared when the TBUF data word is transferred to the transmit shift register.
// - EOF = 1b : The data word in TBUF is considered as last word of an SSC frame.
// - TDSSM = 1b : TBUF Data Single Shot Mode: data in TBUf is considered inactive after being moved into the shift register, send data only once.
// - TDEN = 01b: TBUF Data Enable : A transmission of the data word in TBUF can be started if bit TDV = 1.
// ------------------------------------------------------------
// TDEN TDSSM
SPI_CH->TCSR = (1 << 10) |(1 << 8);
// ------------------------------------------------------------
// ------------------------------------------------------------
// 6.Configure SSC protocol-specific parameters : SSC PCR Protocol Control Register RM 18.4.5.1
// - Slave select generation is enabled : MSLSEN = 1
// - Direct slave select mode is selected
// - End of frame condition is required for the frame to be
// considered as finished
// - SELO0 is selected as the active select signal with (1<<16)
// - SELO2 with (1<<18)
// - CTQSEL1 = 0b10 = 2 -> fCTQIN = fsclk
// - PCTQ1 = 0 and DCTQ1 = 9 -> delay 10 us for fsclk = 1 Mbit/sec
// - PCTQ1 = 1 and DCTQ1 = 23 -> delay 6 us for fsclk = 8 Mbit/sec
// ------------------------------------------------------------
// TIWEN SELO SELCTR MSLSEN CTQSEL1 DCTQ1 PCTQ1
SPI_CH->PCR = (1 << 24 ) | (1<<16) | (1<<1) | (1<<0) | (2<<4) | (23<<8) | (1<<6);
// ------------------------------------------------------------
// ------------------------------------------------------------
// 7.Enable SSC protocol
// ------------------------------------------------------------
// MODE
SPI_CH->CCR = (1 << 0);
//================================================
// U0C0
// INPUT - MISO - P5.0 - USIC0_CH0.DX0D -> P5_IOCR0 -> PC0 -> bits [7-3]
// DX0D : change Input control register
//PORT5->IOCR0 |= 0b00000000000000000000000000000000; // direct input, no internal pull device active
// OUTPUT - MOSI - P1.5 - USIC0_CH0.DOUT0 -> P1_IOCR4 -> PC5 ( because P1.5) -> bits [15-11]
// U0C0.DOUT0
// Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT1->IOCR4 |= 0b00000000000000001001000000000000;
//CLK - P0.8 -> P0_IOCR8 -> PC8 -> bits [7-3]
// USIC0_CH0.SCLKOUT
//Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT0->IOCR8 |= 0b00000000000000000000000010010000;
// Slave Select SELO0 - P0.7
// P0.7 -> P0_IOCR4 -> PC7 -> bits [31-27]
// SELO0 -> Check PCR register
// Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT0->IOCR4 |= 0b10010000000000000000000000000000;
Thank you in advance,
Nicolas Show Less
XMC™
Hello,im looking for an example of watchdog register settings (without DAVE-apps and without XMC-lib).I tried the implementation of the Dave3 app "WDT...
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Hello,
im looking for an example of watchdog register settings (without DAVE-apps and without XMC-lib).
I tried the implementation of the Dave3 app "WDT001" but the watchdog isn't running.
Here my try:
/* Backup Clock */
#define CLK001_WDTCLK_BACKUP 0UL
/* Standby Clock */
#define CLK001_WDTCLK_STANDBY 1UL
/* PLL Clock (fPLL) */
#define CLK001_WDTCLK_PLL 2U
#define CLK001_WDT_CLKSRC CLK001_WDTCLK_BACKUP
#define WDT001_Enable() (WDT->CTR |= (uint32_t)1 << WDT_CTR_ENB_Pos)
#define PER2_WDT 0x20000002U
/** Clear BitMask */
#define CLEAR_BITMASK 0xF0000000U
/** Reset BitMask */
#define RESET_BITMASK 0x0FFFFFFFU
//WDT-INIT
uint32_t* RCUControlReg = 0 ;
uint32_t Temp = 0 ;
/* <<>> */
SCU_RESET_TypeDef* RCUCtrlReg = SCU_RESET;
Temp = ((uint32_t)PER2_WDT & CLEAR_BITMASK) >> 28;
RCUControlReg = (uint32_t*)((uint32_t)(&RCUCtrlReg->PRSET0) + ( 0x0000000CU * Temp));
*RCUControlReg = ((uint32_t)PER2_WDT & RESET_BITMASK );
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_RSCLR_Msk;
SCU_CLK->WDTCLKCR |= CLK001_WDTCLKDIV;
/* Select the WDT Clock source */
SCU_CLK->WDTCLKCR =(uint32_t)((uint32_t)CLK001_WDT_CLKSRC << SCU_CLK_WDTCLKCR_WDTSEL_Pos) & SCU_CLK_WDTCLKCR_WDTSEL_Msk;
/* Enable WDT Clock */
SCU_CLK->CLKSET |= (uint32_t)SCU_CLK_CLKSET_WDTCEN_Msk;
/* Configure Window Lower Bound*/
WDT->WLB = 0x0UL;
/* Configure Window Upper Bound*/
WDT->WUB = 0x4ffffffUL;
/* Configure pre-warning interrupt enable
and Service Indication pulse width*/
WDT->CTR |= (uint32_t)\
((((uint32_t)0 << WDT_CTR_SPW_Pos) & WDT_CTR_SPW_Msk) | \
((uint32_t)0 << WDT_CTR_PRE_Pos));
WDT001_Enable();
What is missing?
Regards
Bernd
Show Less
im looking for an example of watchdog register settings (without DAVE-apps and without XMC-lib).
I tried the implementation of the Dave3 app "WDT001" but the watchdog isn't running.
Here my try:
/* Backup Clock */
#define CLK001_WDTCLK_BACKUP 0UL
/* Standby Clock */
#define CLK001_WDTCLK_STANDBY 1UL
/* PLL Clock (fPLL) */
#define CLK001_WDTCLK_PLL 2U
#define CLK001_WDT_CLKSRC CLK001_WDTCLK_BACKUP
#define WDT001_Enable() (WDT->CTR |= (uint32_t)1 << WDT_CTR_ENB_Pos)
#define PER2_WDT 0x20000002U
/** Clear BitMask */
#define CLEAR_BITMASK 0xF0000000U
/** Reset BitMask */
#define RESET_BITMASK 0x0FFFFFFFU
//WDT-INIT
uint32_t* RCUControlReg = 0 ;
uint32_t Temp = 0 ;
/* <<
SCU_RESET_TypeDef* RCUCtrlReg = SCU_RESET;
Temp = ((uint32_t)PER2_WDT & CLEAR_BITMASK) >> 28;
RCUControlReg = (uint32_t*)((uint32_t)(&RCUCtrlReg->PRSET0) + ( 0x0000000CU * Temp));
*RCUControlReg = ((uint32_t)PER2_WDT & RESET_BITMASK );
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_RSCLR_Msk;
SCU_CLK->WDTCLKCR |= CLK001_WDTCLKDIV;
/* Select the WDT Clock source */
SCU_CLK->WDTCLKCR =(uint32_t)((uint32_t)CLK001_WDT_CLKSRC << SCU_CLK_WDTCLKCR_WDTSEL_Pos) & SCU_CLK_WDTCLKCR_WDTSEL_Msk;
/* Enable WDT Clock */
SCU_CLK->CLKSET |= (uint32_t)SCU_CLK_CLKSET_WDTCEN_Msk;
/* Configure Window Lower Bound*/
WDT->WLB = 0x0UL;
/* Configure Window Upper Bound*/
WDT->WUB = 0x4ffffffUL;
/* Configure pre-warning interrupt enable
and Service Indication pulse width*/
WDT->CTR |= (uint32_t)\
((((uint32_t)0 << WDT_CTR_SPW_Pos) & WDT_CTR_SPW_Msk) | \
((uint32_t)0 << WDT_CTR_PRE_Pos));
WDT001_Enable();
What is missing?
Regards
Bernd
XMC™
Hi all,I am trying to configure the DMA module to read 3 ADC registers and transfer their contents into an array. It is similar to what is described i...
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Hi all,
I am trying to configure the DMA module to read 3 ADC registers and transfer their contents into an array. It is similar to what is described in the following App. Note: http://www.infineon.com/dgdl/Infineon-GPDMA-XMC4000-AP32290-AN-v01_00-EN.pdf?fileId=5546d4624e765da5014ed9145c601e95, Multi block transfer of VADC result registers to RAM for
motor control.
In short, I configured the ADC to take 8 samples, which are distributed among 3 result registers (accumulation mode is ON). When the last conversion is completed and the result becomes available, an SR trigger is fired (e.g. G0SR1) to indicate the availability of all the results. This trigger is routed to GPDMA0, Channel 0, which is configured as follows:
In my understanding, what would happen is as follows:
(a) The DMA would look at VADC_G0->RES[1] (which it does properly, by the way, but I will elaborate on this a little later), take the value from that register and transfer it to variables[0]
(b) The source address would increment by 32 bits (because of gather settings), and would point at VADC_G0->RES[2]
(c) The destination address would increment by 16 bits and would point to variables[1] (Note: variables is an array of type uint16_t)
(d) This process would repeat, starting from (a), but for VADC_G0->RES[2]
However, the problem is that the DMA stalls once it has transferred the values out of RES[1] to variables[0]. In other words, when I look at the RES registers, I can see that the valid flag (VF) of RES[1] is cleared, meaning that the DMA has read that register. Also, a new value appears in variables[0]. But RES[2] and RES[3] both have their valid flags set to 1, i.e. VF = 1, meaning that the DMA has never read those registers.
One more observation that might help - if I remove wait_for_read_mode = 1 from result configuration registers, then DMA seems to work as it should, or at least transfer some values into variables[1] and variables[2]. Can it be that the first block transfer is different from the rest somehow?
Could someone please shed some light on this problem? Cheers!
Best regards,
Andrey
Show Less
I am trying to configure the DMA module to read 3 ADC registers and transfer their contents into an array. It is similar to what is described in the following App. Note: http://www.infineon.com/dgdl/Infineon-GPDMA-XMC4000-AP32290-AN-v01_00-EN.pdf?fileId=5546d4624e765da5014ed9145c601e95, Multi block transfer of VADC result registers to RAM for
motor control.
In short, I configured the ADC to take 8 samples, which are distributed among 3 result registers (accumulation mode is ON). When the last conversion is completed and the result becomes available, an SR trigger is fired (e.g. G0SR1) to indicate the availability of all the results. This trigger is routed to GPDMA0, Channel 0, which is configured as follows:
XMC_DMA_CH_CONFIG_t dma0_config_channel0 = {
.enable_interrupt = false,
.dst_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.src_transfer_width = XMC_DMA_CH_TRANSFER_WIDTH_16,
.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
.dst_burst_length = XMC_DMA_CH_BURST_LENGTH_1, /* TRANSACTION LENGTH - not applicable for memory transfers; memory transfers are limited by AHB transfer size */
.src_burst_length = XMC_DMA_CH_BURST_LENGTH_1,
.enable_dst_scatter = false, /* Target variables are 16 bit */
.enable_src_gather = true, /* To get 16-bit result from 32-bit register */
.src_gather_interval = 1U,
.src_gather_count = 1U,
.dst_scatter_interval = 0U,
.dst_scatter_count = 0U,
.block_size = 3U,
.transfer_flow = XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
.src_addr = (uint32_t) &(VADC_G0->RES[1]),
.dst_addr = (uint32_t) &variables[0],
.transfer_type = XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD,
.priority = XMC_DMA_CH_PRIORITY_7,
.src_handshaking = XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
.src_peripheral_request = DMA0_PERIPHERAL_REQUEST_VADC_G0SR1_4
};
In my understanding, what would happen is as follows:
(a) The DMA would look at VADC_G0->RES[1] (which it does properly, by the way, but I will elaborate on this a little later), take the value from that register and transfer it to variables[0]
(b) The source address would increment by 32 bits (because of gather settings), and would point at VADC_G0->RES[2]
(c) The destination address would increment by 16 bits and would point to variables[1] (Note: variables is an array of type uint16_t)
(d) This process would repeat, starting from (a), but for VADC_G0->RES[2]
However, the problem is that the DMA stalls once it has transferred the values out of RES[1] to variables[0]. In other words, when I look at the RES
One more observation that might help - if I remove wait_for_read_mode = 1 from result configuration registers, then DMA seems to work as it should, or at least transfer some values into variables[1] and variables[2]. Can it be that the first block transfer is different from the rest somehow?
Could someone please shed some light on this problem? Cheers!
Best regards,
Andrey
XMC™
Hi all,I want to read the register NVIC_ISER to check if an interrupt is enabled or not but I am not sure how to do that. Do I use RD_REG()? If yes, w...
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Hi all,
I want to read the register NVIC_ISER to check if an interrupt is enabled or not but I am not sure how to do that. Do I use RD_REG()? If yes, what should I pass as paramter? NVIC_ISERx?
Thanks,
Ahmed Show Less
I want to read the register NVIC_ISER to check if an interrupt is enabled or not but I am not sure how to do that. Do I use RD_REG()? If yes, what should I pass as paramter? NVIC_ISERx?
Thanks,
Ahmed Show Less
XMC™
I tried to use the Timer Apps to get the current time since the timer is started, but it doesn’t seem working;Look at the following code :Inside the i...
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I tried to use the Timer Apps to get the current time since the timer is started, but it doesn’t seem working;
Look at the following code :
Inside the infinite loop, the value elapsedTime receive the result of TIMER_GetTime(&TIMER_0).
It should increase at each loop right ? However, at the third loop, the value decrease, and increase again.
I configured the App with CCU8, a time interval of 1000 us, and no time interval event.
I don’t need to generate event, but I don’t know how to choose the timer resolution (From 0 to 1 count, the time taken is 1ms for example).
With a time interval of 1000 us, I have the following :
initTime = 119
timerRunning = 1
1. elapsedTime = 62730
2. elapsedTime = 2844
3. elapsedTime = 40827
4. elapsedTime = 41261
5. elapsedTime = 13538
The result should increase at each loop, or it seem random.
Any help please ?
Nicolas Show Less
Look at the following code :
Inside the infinite loop, the value elapsedTime receive the result of TIMER_GetTime(&TIMER_0).
It should increase at each loop right ? However, at the third loop, the value decrease, and increase again.
I configured the App with CCU8, a time interval of 1000 us, and no time interval event.
I don’t need to generate event, but I don’t know how to choose the timer resolution (From 0 to 1 count, the time taken is 1ms for example).
With a time interval of 1000 us, I have the following :
initTime = 119
timerRunning = 1
1. elapsedTime = 62730
2. elapsedTime = 2844
3. elapsedTime = 40827
4. elapsedTime = 41261
5. elapsedTime = 13538
The result should increase at each loop, or it seem random.
int main(void)
{
DAVE_STATUS_t status;
TIMER_STATUS_t timer_status;
uint32_t initTime;
uint32_t elapsedTime;
uint32_t i,j,k = 0;
uint32_t test = 0;
uint8_t timerRunning = 0;
status = DAVE_Init(); /* Initialization of DAVE APPs */
if(status != DAVE_STATUS_SUCCESS)
{
/* Placeholder for error handler code. The while loop below can be replaced with an user error handler. */
XMC_DEBUG("DAVE APPs initialization failed\n");
while(1U)
{
}
}
TIMER_Start(&TIMER_0);
if ( TIMER_GetTimerStatus(&TIMER_0)) // TIMER_GetTimerStatus(&TIMER_0) : return true = timer is running
{
initTime = TIMER_GetTime(&TIMER_0);
timerRunning = 1;
}
/* Placeholder for user application code. The while loop below can be replaced with user application code. */
while(1U)
{
j = 0;
for (i=0; i<365000; i++)
{
j = i+1;
}
j = 0;
elapsedTime = TIMER_GetTime(&TIMER_0);
}
}
Any help please ?
Nicolas Show Less
XMC™
Hi,I have a question for the more xperienced users here; when I use the App USBD_VCOM, does the pin 0.10 get assigned to something? I have a button co...
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Hi,
I have a question for the more xperienced users here; when I use the App USBD_VCOM, does the pin 0.10 get assigned to something? I have a button connected to that pin and set up with an interrupt and when I initialise USBD_VCOM the interrupt stops firing although the signal still stands.
Thanks,
Ahmed Show Less
I have a question for the more xperienced users here; when I use the App USBD_VCOM, does the pin 0.10 get assigned to something? I have a button connected to that pin and set up with an interrupt and when I initialise USBD_VCOM the interrupt stops firing although the signal still stands.
Thanks,
Ahmed Show Less
XMC™
Hello all,
I have a quick questions, what Pin is the signal VAGND assigned to? Or is that connected to GND?
Cheers,
Ahmed
I have a quick questions, what Pin is the signal VAGND assigned to? Or is that connected to GND?
Cheers,
Ahmed
XMC™
Hello,I am using DACWG001 in Singe Value mode to output an analog voltage. However, the DAC is setting crazy voltages:Input | Output0 |...
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Hello,
I am using DACWG001 in Singe Value mode to output an analog voltage. However, the DAC is setting crazy voltages:
Input | Output
0 | 0.3 (correct)
1000 | 1.7 (incorrect)
2000 | 0.8 (incorrect)
2500 | 0.4 (incorrect)
2550 | 2.1 (incorrect)
2600 | 1.7 (correct)
2650 | 1.2 (incorrect)
3000 | 2.2 (incorrect)
4095 | 2.4 (incorrect)
Has anyone else encountered the same problem and know if I'm the one doing something wrong?
EDIT: I have found out what I was doing wrong; in scale I thought 1 means multiplying with 1 but turns out it's 2^1, my bad. While that doesn't explain the weird voltage levels, now that I set it at 0 everythings's fine. Show Less
I am using DACWG001 in Singe Value mode to output an analog voltage. However, the DAC is setting crazy voltages:
Input | Output
0 | 0.3 (correct)
1000 | 1.7 (incorrect)
2000 | 0.8 (incorrect)
2500 | 0.4 (incorrect)
2550 | 2.1 (incorrect)
2600 | 1.7 (correct)
2650 | 1.2 (incorrect)
3000 | 2.2 (incorrect)
4095 | 2.4 (incorrect)
Has anyone else encountered the same problem and know if I'm the one doing something wrong?
EDIT: I have found out what I was doing wrong; in scale I thought 1 means multiplying with 1 but turns out it's 2^1, my bad. While that doesn't explain the weird voltage levels, now that I set it at 0 everythings's fine. Show Less
XMC™
Hello,I'm wondering what the MAC address of my Relax board is.Is it defined in the XMC4500 or in the PHY? Or is there no "official" MAC address, so wh...
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Hello,
I'm wondering what the MAC address of my Relax board is.
Is it defined in the XMC4500 or in the PHY? Or is there no "official" MAC address, so which should I take then?
Thank you in advance.
Best regards
Lonz Show Less
I'm wondering what the MAC address of my Relax board is.
Is it defined in the XMC4500 or in the PHY? Or is there no "official" MAC address, so which should I take then?
Thank you in advance.
Best regards
Lonz Show Less
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