XMC™ Forum Discussions
XMC™
I am using tm4c123g and ds1307 to display time (hh:mm:ss) on sevensegments and date and day on lcd(16x2). IS there any way way to use same 8 pins for ...
Show More
I am using tm4c123g and ds1307 to display time (hh:mm:ss) on sevensegments and date and day on lcd(16x2).
IS there any way way to use same 8 pins for data of both (lcd and seven segment display..as they are to diplay different data).
Can time multiplexing be used for that purpose? Tell me any idea or any way to do this... Show Less
IS there any way way to use same 8 pins for data of both (lcd and seven segment display..as they are to diplay different data).
Can time multiplexing be used for that purpose? Tell me any idea or any way to do this... Show Less
XMC™
HelloI am trying to use emWin with XMC4500-F100x1024.The Flash size for this MCU is 1Mb and RAM size is 160k.My Display is 800x480 , and my driver is ...
Show More
Hello
I am trying to use emWin with XMC4500-F100x1024.
The Flash size for this MCU is 1Mb and RAM size is 160k.
My Display is 800x480 , and my driver is SSD1963 in 16-bit parallel RGB565 mode.
I am having troubles with the emWin library which I have posted elsewhere.
On my board I have a QSPI N25Q032 from Micron as an external flash.
My Goal :
I want to store all images, Fonts and any memory hungry resources required by emWin to this Flash.
EmWin should fetch these images/fonts/gif etc. from the Flash and draw them to the TFT.
What I can achieve till now:
I can read and write to the flash in 256 byte page size and read it, but all values are hex values.
Problem statement:
EmWin requires images which it renders, stored as a C-file, included at compile time in local flash.
I use BMPconvert images to C-files.
I include these files and I have no problem drawing these on the TFT.
I am planning to store these images to the external flash during run time over a USB communication interface of XMC4500. A Windows based software will talk with the XMC4500 for this.
I know how to transfer data over USB, but unsure how to transfer a C-file likewise.
I don’t know how emWin would fetch this data from the external flash at runtime.
EmWin requires more RAM, it seems since most of transparency, multilayer and alpha blending functions have never worked for me.
In the GUI_SEGGERLIBRARY app, if I enable the cache for non-readable display, emWin crashes. Perhaps there is insufficient memory.
I am trying to use GUI_DrawStreamedBitmap() but not able to understand how it can used in my case where the data to be streamed is under another protocol layer (QSPI).
I have been running from pillar to post but unable to understand or resolve this.
Please help me. Show Less
I am trying to use emWin with XMC4500-F100x1024.
The Flash size for this MCU is 1Mb and RAM size is 160k.
My Display is 800x480 , and my driver is SSD1963 in 16-bit parallel RGB565 mode.
I am having troubles with the emWin library which I have posted elsewhere.
On my board I have a QSPI N25Q032 from Micron as an external flash.
My Goal :
I want to store all images, Fonts and any memory hungry resources required by emWin to this Flash.
EmWin should fetch these images/fonts/gif etc. from the Flash and draw them to the TFT.
What I can achieve till now:
I can read and write to the flash in 256 byte page size and read it, but all values are hex values.
Problem statement:
EmWin requires images which it renders, stored as a C-file, included at compile time in local flash.
I use BMPconvert images to C-files.
I include these files and I have no problem drawing these on the TFT.
I am planning to store these images to the external flash during run time over a USB communication interface of XMC4500. A Windows based software will talk with the XMC4500 for this.
I know how to transfer data over USB, but unsure how to transfer a C-file likewise.
I don’t know how emWin would fetch this data from the external flash at runtime.
EmWin requires more RAM, it seems since most of transparency, multilayer and alpha blending functions have never worked for me.
In the GUI_SEGGERLIBRARY app, if I enable the cache for non-readable display, emWin crashes. Perhaps there is insufficient memory.
I am trying to use GUI_DrawStreamedBitmap() but not able to understand how it can used in my case where the data to be streamed is under another protocol layer (QSPI).
I have been running from pillar to post but unable to understand or resolve this.
Please help me. Show Less
XMC™
Hi,I have read the reference manual in order to understand if it's possible to set up the USIC module on a XMC4500 for RS232 with flow control "RTS/CT...
Show More
Hi,
I have read the reference manual in order to understand if it's possible to set up the USIC module on a XMC4500 for RS232 with flow control "RTS/CTS (RTR/CTS)". However, I not been able to understand whether it's possible or not so I would really appreciate some hints here. Hopefully somebody has experience from a similar setup or other useful information..?
For instance:
- Can DX1/DX2 stages be used for "CTS"?
- How can I generate a "RTR"?
Best regards,
Johan Show Less
I have read the reference manual in order to understand if it's possible to set up the USIC module on a XMC4500 for RS232 with flow control "RTS/CTS (RTR/CTS)". However, I not been able to understand whether it's possible or not so I would really appreciate some hints here. Hopefully somebody has experience from a similar setup or other useful information..?
For instance:
- Can DX1/DX2 stages be used for "CTS"?
- How can I generate a "RTR"?
Best regards,
Johan Show Less
XMC™
Hi,How can i program the EEPROM which connected to EtherCAT slave(XMC4300) from a master side(TwinCAT)?Any example/guideline?:oThank youRegards,Herry
Show More
Hi,
How can i program the EEPROM which connected to EtherCAT slave(XMC4300) from a master side(TwinCAT)?
Any example/guideline?:o
Thank you
Regards,
Herry Show Less
How can i program the EEPROM which connected to EtherCAT slave(XMC4300) from a master side(TwinCAT)?
Any example/guideline?:o
Thank you
Regards,
Herry Show Less
XMC™
Hello Forum.Well, I'm becoming quiet dependent on this forum. I am trying to do something very similar to what is outlined in the application note AP...
Show More
Hello Forum.
Well, I'm becoming quiet dependent on this forum.
I am trying to do something very similar to what is outlined in the application note AP32287 section 4.2: Example use case: triggering ADC conversion using CCU4 single shot.
I trigger the CCU4 by an event not a push button.
The CCU4 trigger is working because I CC4yINTS status shows that a period match was detected AND an event 0 was detected.
And the CC4ySRS register is configured for forward Event 0 Service requests to CC4ySR2 which is hooked up to ADC input selector.
I have the ADC queue ready to receive the trigger event and start doing it's conversion, and I think it does it, but I get no interrupt at the end.
I think the ADC is getting it because if I configure the queue to not refill, I get a QUEUE EMPTY in the QSR0.
Any pointers would be great....
Here is my code snips...
Right after the XMC_SCU_SetCcuTriggerHigh(..) I'm expecting the interrupt to hit.
Again, any help would be really appreciated.
-Steve Show Less
Well, I'm becoming quiet dependent on this forum.
I am trying to do something very similar to what is outlined in the application note AP32287 section 4.2: Example use case: triggering ADC conversion using CCU4 single shot.
I trigger the CCU4 by an event not a push button.
The CCU4 trigger is working because I CC4yINTS status shows that a period match was detected AND an event 0 was detected.
And the CC4ySRS register is configured for forward Event 0 Service requests to CC4ySR2 which is hooked up to ADC input selector.
I have the ADC queue ready to receive the trigger event and start doing it's conversion, and I think it does it, but I get no interrupt at the end.
I think the ADC is getting it because if I configure the queue to not refill, I get a QUEUE EMPTY in the QSR0.
Any pointers would be great....
Here is my code snips...
/* ADC */
#define RES_REG_NUMBER (0)
#define CHANNEL_NUMBER (2U)
#define VADC_GROUP_PTR (VADC_G0) /* P14.2 */
#define VADC_GROUP_ID (0)
#define IRQ_PRIORITY (10U)
/* CCU4 */
#define SLICE_PTR CCU40_CC43
#define MODULE_PTR CCU40
#define MODULE_NUMBER (0U)
#define SLICE_NUMBER (3U)
#define CAPCOM_MASK (SCU_GENERAL_CCUCON_GSC40_Msk)
/* ADC */
XMC_VADC_GLOBAL_CONFIG_t g_global_handle =
{
.disable_sleep_mode_control = false,
.clock_config = {
.analog_clock_divider = 3,
.msb_conversion_clock = 0,
.arbiter_clock_divider = 1
},
.class0 = {
.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
.sample_time_std_conv = 3U,
.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
.sampling_phase_emux_channel = 3U
},
.class1 = {
.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
.sample_time_std_conv = 3U,
.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
.sampling_phase_emux_channel = 3U
},
.data_reduction_control = 0,
.wait_for_read_mode = true,
.event_gen_enable = false,
.boundary0 = 0,
.boundary1 = 0
};
XMC_VADC_GROUP_CONFIG_t g_group_handle = {
.class0 = {
.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
.sample_time_std_conv = 3U,
.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
.sampling_phase_emux_channel = 3U
},
.class1 = {
.conversion_mode_standard = XMC_VADC_CONVMODE_12BIT,
.sample_time_std_conv = 3U,
.conversion_mode_emux = XMC_VADC_CONVMODE_12BIT,
.sampling_phase_emux_channel = 3U
},
.arbitration_round_length = 0x0U,
.arbiter_mode = XMC_VADC_GROUP_ARBMODE_ALWAYS,
.boundary0 = 0,
.boundary1 = 0,
.emux_config = {
.emux_mode = XMC_VADC_GROUP_EMUXMODE_SWCTRL,
.stce_usage = 0,
.emux_coding = XMC_VADC_GROUP_EMUXCODE_BINARY,
.starting_external_channel = 0,
.connected_channel = 0
}
};
XMC_VADC_GROUP_t *g_group_identifier = VADC_GROUP_PTR;
XMC_VADC_CHANNEL_CONFIG_t g_channel_handle =
{
.channel_priority = 1U,
.input_class = XMC_VADC_CHANNEL_CONV_GROUP_CLASS1,
.alias_channel = -1,
.bfl = 0,
.event_gen_criteria = XMC_VADC_CHANNEL_EVGEN_ALWAYS,
.alternate_reference = XMC_VADC_CHANNEL_REF_INTREF,
.result_reg_number = (uint8_t) RES_REG_NUMBER,
.use_global_result = false,
.broken_wire_detect_channel = false,
.broken_wire_detect = false
};
XMC_VADC_RESULT_CONFIG_t g_result_handle = {
.post_processing_mode = XMC_VADC_DMM_REDUCTION_MODE,
.data_reduction_control = 0,
.part_of_fifo = false,
.wait_for_read_mode = true,
.event_gen_enable = false
};
/* Queue hardware configuration data */
XMC_VADC_QUEUE_CONFIG_t g_queue_handle =
{
.req_src_priority = (uint8_t)3, /* 3 = highest, 0 = lowest */
.conv_start_mode = XMC_VADC_STARTMODE_WFS,
.external_trigger = (bool) true, /* external trigger enabled */
.trigger_signal = XMC_CCU_40_SR2,
.trigger_edge = XMC_VADC_TRIGGER_EDGE_ANY,
.gate_signal = XMC_VADC_REQ_GT_A,
.timer_mode = (bool) false /* no timer mode */
};
XMC_VADC_QUEUE_ENTRY_t g_queue_entry =
{
.channel_num = CHANNEL_NUMBER,
.refill_needed = true,
.generate_interrupt = true,
.external_trigger = true
};
/* CCU4 */
XMC_CCU4_SLICE_COMPARE_CONFIG_t g_timer_object =
{
.timer_mode = XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA,
.monoshot = true,
.shadow_xfer_clear = 0U,
.dither_timer_period = 0U,
.dither_duty_cycle = 0U,
.prescaler_mode = XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL,
.mcm_enable = 0U,
.prescaler_initval = 0U,
.float_limit = 0U,
.dither_limit = 0U,
.passive_level = XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW,
.timer_concatenation = 0U
};
/* CCU Slice Capture Initialization Data */
XMC_CCU4_SLICE_CAPTURE_CONFIG_t g_capture_object =
{
.fifo_enable = false,
.timer_clear_mode = XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER,
.same_event = false,
.ignore_full_flag = false,
.prescaler_mode = XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL,
.prescaler_initval = 0,
.float_limit = 0,
.timer_concatenation = false
};
void ConifgureADC(void)
{
/* init VADC global registers */
XMC_VADC_GLOBAL_Init(VADC,&g_global_handle);
/* Configure a conversion kernel */
XMC_VADC_GROUP_Init(g_group_identifier, &g_group_handle);
/* Configure the queue request source of the aforsaid conversion kernel */
XMC_VADC_GROUP_QueueInit(g_group_identifier,&g_queue_handle);
/* Configure the channel belong to aforesaid conversion kernel */
XMC_VADC_GROUP_ChannelInit(g_group_identifier,CHANNEL_NUMBER,&g_channel_handle);
/* Conifgure a result resource belonging to the aforesaid conversion kernel */
XMC_VADC_GROUP_ResultInit(g_group_identifier, RES_REG_NUMBER, &g_result_handle);
/* Add the channel to the queue */
XMC_VADC_GROUP_QueueInsertChannel(g_group_identifier, g_queue_entry);
/* Connect RS Event to the NVICE nodes */
XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode(g_group_identifier, XMC_VADC_SR_GROUP_SR0);
/* Config the NVIC */
/* Set Priority */
NVIC_SetPriority(VADC0_G0_3_IRQn,IRQ_PRIORITY);
/* Enable */
NVIC_EnableIRQ(VADC0_G0_3_IRQn);
/* enabled the analog converters */
XMC_VADC_GROUP_SetPowerMode(g_group_identifier,XMC_VADC_GROUP_POWERMODE_NORMAL);
/* Perform calibration of the converter */
XMC_VADC_GLOBAL_StartupCalibration(VADC);
}
/* CCU4 */
XMC_CCU4_SLICE_EVENT_CONFIG_t config;
config.duration = XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES;
config.edge = XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE;
config.level = XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH; /* Not needed */
config.mapped_input = XMC_CCU4_SLICE_INPUT_I;
/* Enable clock, enable prescaler block and configure global control */
XMC_CCU4_Init(MODULE_PTR, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR);
/* Start the prescaler and restore clocks to slices */
XMC_CCU4_StartPrescaler(MODULE_PTR);
/* Ensure fCCU reaches CCU40 */
XMC_CCU4_SetModuleClock(MODULE_PTR, XMC_CCU4_CLOCK_SCU);
/* Initialize the Slice */
XMC_CCU4_SLICE_CompareInit(SLICE_PTR, &g_timer_object);
/* Set a duty cycle [33.3%] and frequency of [24kHz] */
XMC_CCU4_SLICE_SetTimerCompareMatch(SLICE_PTR,1777);
XMC_CCU4_SLICE_SetTimerPeriodMatch(SLICE_PTR, 2665U);
XMC_CCU4_SLICE_EnableEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);
XMC_CCU4_SLICE_EnableEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP);
/* Enable shadow transfer for PWM Slice */
XMC_CCU4_EnableShadowTransfer(MODULE_PTR,(uint32_t)XMC_CCU4_SHADOW_TRANSFER_SLICE_3);
/* Configure events -- Start */
/* Configure Event-1 and map it to Input-I */
XMC_CCU4_SLICE_ConfigureEvent(SLICE_PTR, XMC_CCU4_SLICE_EVENT_0, &config);
/* Map Event-1 to Start function */
XMC_CCU4_SLICE_StartConfig(SLICE_PTR, XMC_CCU4_SLICE_EVENT_0, XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR);
/* Enable events */
XMC_CCU4_SLICE_EnableEvent(SLICE_PTR, XMC_CCU4_SLICE_IRQ_ID_EVENT0);
/* Connect the event to SR2, which is the ADC */
XMC_CCU4_SLICE_SetInterruptNode(SLICE_PTR,XMC_CCU4_SLICE_IRQ_ID_EVENT0,XMC_CCU4_SLICE_SR_ID_2);
/* Take SLICE out of idle mode */
XMC_CCU4_EnableClock(MODULE_PTR,SLICE_NUMBER);
XMC_SCU_SetCcuTriggerHigh(CAPCOM_MASK);
while(1);
}
Right after the XMC_SCU_SetCcuTriggerHigh(..) I'm expecting the interrupt to hit.
Again, any help would be really appreciated.
-Steve Show Less
XMC™
I try to receive CAN messages with 2 different CAN-Ids on a XMC4500. I have configured 2 message objects, allocated them to the Node list, configured ...
Show More
I try to receive CAN messages with 2 different CAN-Ids on a XMC4500. I have configured 2 message objects, allocated them to the Node list, configured and enabled 2 IRQHandlers and am able to receive messages with both IDs correctly.
Important parts of the configuration:
Here's the interrupt handler:
But, the following sequence leads to an exception:
- receiving message A and sending response
- receiving message B: call to XMC_CAN_MO_ResetStatus() leads to an exception, because RxMsgObj is empty (0). The interrupt handler is called over and over again, with no ne data available.
Question:
What is the correct method to get the data of a received message, copy it to my own Message Queue and acknowledge/reset the message object/interrupt?
Could anyone post a "best practice example"?
(I studied the XMCLIB docu, but it's not very helpful, only describes the individual functions, but not whích one to use in which order. Also, a search of forums and Google didn't help. PS: I have to find a solution without APPs due to performance reasons)
Any hints welcome! Thanks a lot!
Jyrki Show Less
Important parts of the configuration:
XMC_CAN_MO_t RxMsgObj =
{
.can_mo_type = XMC_CAN_MO_TYPE_RECMSGOBJ,
.can_id_mode = XMC_CAN_FRAME_TYPE_STANDARD_11BITS,
.can_priority = XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1,
.can_identifier = (uint32_t)0x750,
.can_id_mask = (uint32_t)0x7AF,
.can_ide_mask = 1U,
.can_mo_ptr = (CAN_MO_TypeDef*)CAN_MO1,
.can_data_length = (uint8_t)8,
.can_data[1] = 0, // auch über can_data_byte[0..7] zugreifbar!
.can_data[0] = 0
};
[...]
XMC_CAN_AllocateMOtoNodeList((CAN_GLOBAL_TypeDef*)CAN, CAN_CFG_NODE_NUM, 1); // MO 1
XMC_CAN_AllocateMOtoNodeList((CAN_GLOBAL_TypeDef*)CAN, CAN_CFG_NODE_NUM, 2); // MO 2
XMC_CAN_MO_Config(&RxMsgObj);
XMC_CAN_MO_Config(&RxMsgObj2);
XMC_CAN_MO_SetEventNodePointer(&RxMsgObj, XMC_CAN_MO_POINTER_EVENT_RECEIVE, 7);
XMC_CAN_MO_SetEventNodePointer(&RxMsgObj2, XMC_CAN_MO_POINTER_EVENT_RECEIVE, 6);
NVIC_SetPriority(CAN0_7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
NVIC_SetPriority(CAN0_6_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 62U, 0U));
NVIC_EnableIRQ(CAN0_7_IRQn);
NVIC_EnableIRQ(CAN0_6_IRQn);
XMC_CAN_NODE_DisableConfigurationChange(CAN_CFG_NODE);
XMC_CAN_NODE_ResetInitBit(CAN_CFG_NODE);
Here's the interrupt handler:
void CAN0_7_IRQHandler(void) // Handler for message A (the handler for message B is similar, but with RxMsgObj2)
{
uint32 ulMOStatus;
/* CAN-Buffer 1 ------------------------------------*/
ulMOStatus = XMC_CAN_MO_GetStatus(&RxMsgObj);
if(ulMOStatus & XMC_CAN_MO_STATUS_NEW_DATA)
{
gMsgQueue.ucWriteIdx++;
if(gMsgQueue.ucWriteIdx > CAN_MSG_QUEUE_SIZE - 1)
gMsgQueue.ucWriteIdx = 0;
XMC_CAN_MO_Receive(&RxMsgObj);
gMsgQueue.asMsg[gMsgQueue.ucWriteIdx].ulId = RxMsgObj.can_identifier;
memcpy(&gMsgQueue.asMsg[gMsgQueue.ucWriteIdx].aucData[0], &RxMsgObj.can_data_byte[0], 8);
XMC_CAN_MO_ResetStatus(&RxMsgObj, XMC_CAN_MO_RESET_STATUS_NEW_DATA); // TODO: Leads to an exception sometimes
}
}
But, the following sequence leads to an exception:
- receiving message A and sending response
- receiving message B: call to XMC_CAN_MO_ResetStatus() leads to an exception, because RxMsgObj is empty (0). The interrupt handler is called over and over again, with no ne data available.
Question:
What is the correct method to get the data of a received message, copy it to my own Message Queue and acknowledge/reset the message object/interrupt?
Could anyone post a "best practice example"?
(I studied the XMCLIB docu, but it's not very helpful, only describes the individual functions, but not whích one to use in which order. Also, a search of forums and Google didn't help. PS: I have to find a solution without APPs due to performance reasons)
Any hints welcome! Thanks a lot!
Jyrki Show Less
XMC™
I am using a CCU4 as a PWM.I have set the passive_level in the ccu4SliceConfig to XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW and the GPIO configuration o...
Show More
I am using a CCU4 as a PWM.
I have set the passive_level in the ccu4SliceConfig to XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW and the GPIO configuration output_level ist set to XMC_GPIO_OUTPUT_LEVEL_LOW.
After initialization everything is correct, the PWM is not running and the output is low. I then start the PWM with XMC_CCU4_SLICE_StartTimer().
When I stop the PWM with XMC_CCU4_SLICE_StopTimer() the output remains high.
What do I need to do so that the output is low when the PWM is stopped? Show Less
I have set the passive_level in the ccu4SliceConfig to XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW and the GPIO configuration output_level ist set to XMC_GPIO_OUTPUT_LEVEL_LOW.
After initialization everything is correct, the PWM is not running and the output is low. I then start the PWM with XMC_CCU4_SLICE_StartTimer().
When I stop the PWM with XMC_CCU4_SLICE_StopTimer() the output remains high.
What do I need to do so that the output is low when the PWM is stopped? Show Less
XMC™
We're using the XMC4200 and look to be running into size constraints with the memory. Looking at Memory Settings page in DAVE it shows:Name ...
Show More
We're using the XMC4200 and look to be running into size constraints with the memory. Looking at Memory Settings page in DAVE it shows:
Name Type Start Address End Address Size
PSRAM1 RAM 0x1FFFE000 0x1FFFFFFF 0x2000
DSRAM1 RAM 0x20000000 0x20005FFF 0x6000
So PSRAM1 is 8KB and DSRAM1 is 24KB. We're supposed to have 40KB total and expecting 16KB on PSRAM1 but total is only 32KB.
Can we change the PSRAM1 size to 16KB and if so, what is the addressing we should use?
We notice the DSRAM1 addressing is consecutive with the PSRAM1 addressing so assume we need to change addressing for both.
Thanks Show Less
Name Type Start Address End Address Size
PSRAM1 RAM 0x1FFFE000 0x1FFFFFFF 0x2000
DSRAM1 RAM 0x20000000 0x20005FFF 0x6000
So PSRAM1 is 8KB and DSRAM1 is 24KB. We're supposed to have 40KB total and expecting 16KB on PSRAM1 but total is only 32KB.
Can we change the PSRAM1 size to 16KB and if so, what is the addressing we should use?
We notice the DSRAM1 addressing is consecutive with the PSRAM1 addressing so assume we need to change addressing for both.
Thanks Show Less
XMC™
Hi,I have the problem that flash write operations via the E_EEPROM_XMC1 APP (shipped with Dave 4) sporadically causes irreversible damage to our XMC13...
Show More
Hi,
I have the problem that flash write operations via the E_EEPROM_XMC1 APP (shipped with Dave 4) sporadically causes irreversible damage to our XMC1302 chips.
Our software stores some variables into the flash memory using the mentioned APP upon request. Generally, this is working fine, but three out of eight controllers died after some 10 to 100 write operations. I tried to repair the hardware by erasing and reprogramming the entire chip, but without success.
When I debug the damaged devices through SWD/J-Link, it always shows that the software is stuck in random, unimplemented Interrupt Handlers which should never be entered.
I think that this behavior could be connected to errata NVM_CM.001 "NVM Write access to trigger NVM erase operation must NOT be executed from NVM" and modified the method "void XMC_FLASH_WriteBlocks" in "xmc1_flash.c" to run from SRAM by adding "__attribute__ ((section (".text.fastcode")))".
I tested this modification by executing several thousand write operations on a test device without any problems.
However, I'm not fully convinced that this is really the solution to our problem. Did anybody else experienced such permanent damages through flash operations?
Best regards,
OS1981 Show Less
I have the problem that flash write operations via the E_EEPROM_XMC1 APP (shipped with Dave 4) sporadically causes irreversible damage to our XMC1302 chips.
Our software stores some variables into the flash memory using the mentioned APP upon request. Generally, this is working fine, but three out of eight controllers died after some 10 to 100 write operations. I tried to repair the hardware by erasing and reprogramming the entire chip, but without success.
When I debug the damaged devices through SWD/J-Link, it always shows that the software is stuck in random, unimplemented Interrupt Handlers which should never be entered.
I think that this behavior could be connected to errata NVM_CM.001 "NVM Write access to trigger NVM erase operation must NOT be executed from NVM" and modified the method "void XMC_FLASH_WriteBlocks" in "xmc1_flash.c" to run from SRAM by adding "__attribute__ ((section (".text.fastcode")))".
I tested this modification by executing several thousand write operations on a test device without any problems.
However, I'm not fully convinced that this is really the solution to our problem. Did anybody else experienced such permanent damages through flash operations?
Best regards,
OS1981 Show Less