XMC™ Forum Discussions

Hello,

some Flash routines that worked with the "XMC1302 AA" silicon revision now fail with the "AB" revision. Unfortunately our manufacturer did not notify us, that the new revision was assembled for the lastest batch.

I assume the problem comes from the flash erase cycle.

Current code section:

 // delete complete flash bank
 NVM->NVMPROG = (0x00 << NVM_NVMPROG_ACTION_Pos);  // set prog to 0x00
 NVM->NVMPROG = (NVM_NVMPROG_RSTVERR_Msk | NVM_NVMPROG_RSTECC_Msk);  // clear ECC and Verify Errors
 while(NVM->NVMSTATUS & NVM_NVMSTATUS_BUSY_Msk);   // wait until ready
 NVM->NVMPROG = (0x92 << NVM_NVMPROG_ACTION_Pos);  // set NVM to delete flash (one-shot page erase)
 *write_address = *data_address;                   // write to any address within the bank that should be deleted
 while(NVM->NVMSTATUS & NVM_NVMSTATUS_BUSY_Msk);   // wait until deleting is finished (takes approximately 7 msec)

This is correct according to the latest user manual, too. (Infineon-xmc1300-AB_rm-UM-v01_02-EN.pdf, page 224)
However in the latest errata sheet there is a functional deviation "NVM_CM.001". (Infineon-xmc1300_AB-ES-v01_03-EN.pdf, page 18)
It describes a problem using the low level ERASE routine and suggests usage of a ROM routine.

Is there a code example available using the ROM routines for the flash?

As we have some devices already cast in epoxy I would like to learn a little more about this issue especially about the part "the erase operation is not always executed" (as written in the errata sheet).
There is a small chance to do some bit-level modifications to "repair" the flash write routines on the already enclosed devices. Knowing a little more about the error mechanism will help to decide, if the already enclosed devices are for the trashbin or if a fix is possible.

A quick answer would be nice.

Thanks
Bernd Show Less

Hello,

some Flash routines that worked with the "XMC1302 AA" silicon revision now fail with the "AB" revision. Unfortunately our manufacturer did not notify us, that the new revision was assembled for the lastest batch.

I assume the problem comes from the flash erase cycle.

Current code section:

 // delete complete flash bank
 NVM->NVMPROG = (0x00 << NVM_NVMPROG_ACTION_Pos);  // set prog to 0x00
 NVM->NVMPROG = (NVM_NVMPROG_RSTVERR_Msk | NVM_NVMPROG_RSTECC_Msk);  // clear ECC and Verify Errors
 while(NVM->NVMSTATUS & NVM_NVMSTATUS_BUSY_Msk);   // wait until ready
 NVM->NVMPROG = (0x92 << NVM_NVMPROG_ACTION_Pos);  // set NVM to delete flash (one-shot page erase)
 *write_address = *data_address;                   // write to any address within the bank that should be deleted
 while(NVM->NVMSTATUS & NVM_NVMSTATUS_BUSY_Msk);   // wait until deleting is finished (takes approximately 7 msec)

This is correct according to the latest user manual, too. (Infineon-xmc1300-AB_rm-UM-v01_02-EN.pdf, page 224)
However in the latest errata sheet there is a functional deviation "NVM_CM.001". (Infineon-xmc1300_AB-ES-v01_03-EN.pdf, page 18)
It describes a problem using the low level ERASE routine and suggests usage of a ROM routine.

Is there a code example available using the ROM routines for the flash?

As we have some devices already cast in epoxy I would like to learn a little more about this issue especially about the part "the erase operation is not always executed" (as written in the errata sheet).
There is a small chance to do some bit-level modifications to "repair" the flash write routines on the already enclosed devices. Knowing a little more about the error mechanism will help to decide, if the already enclosed devices are for the trashbin or if a fix is possible.

A quick answer would be nice.

Thanks
Bernd Show Less

Hi,
I have problem while connecting the USB port on XMC4500 relax kit to my laptop. It is not showing the usb vcom port and it is displaying "IFX CDC" with a warning symbol in the device manager.
Please help me to resolve the issue. I am working with windows 8.1. Show Less

Hi,

I'm evaluating xmc1000 (the first Infineon mcu device we've looked at) and have done som initial testing using arm-none-eabi- and Segger gdb server.

Where do i find header files for each device? From what i could see in Dave, device headers files are generated from xml files, but I expect there must be another way to find these header files.

Please do not refer me to the Dave gui (I spent one hour looking at it and concluded it's not worth to waste time on).

Thanks in advance,
MS Show Less

It it possible to use the Relax kit as a USB host?

The Board Users Manual lists "USB-OTG" as a feature, but schematics show that the ID signal is not connected. Show Less

Hello,

I would like to use some GPIOs as additional Slave Select signals. But I do get a timing problem with the gpio slave select signal. it is way faster then the hardware slave select signal. My setup is as following.:

I'm using the XMC Llib to control the USIC, and I'm generating a hardware slave select signal which is not exposed to a pin which sets the MSLS Bit in the PSC register and wait till it is cleared. But it seems that that bit is cleared way to fast by the hardware and so my gpio slave select signal has no chance to accomplish the required timing.

Here is a little sample code which illustrates my problem.

while(1U) {
    XMC_GPIO_SetOutputLow(SOFT_CS);
    XMC_SPI_CH_EnableSlaveSelect(SPI2_CH1, XMC_SPI_CH_SLAVE_SELECT_0);

    XMC_SPI_CH_Transmit(SPI2_CH1, 'A', XMC_SPI_CH_MODE_STANDARD);
    while((XMC_SPI_CH_GetStatusFlag(SPI2_CH1) & XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION) == 0U);
    XMC_SPI_CH_ClearStatusFlag(SPI2_CH1, XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION);

    XMC_SPI_CH_DisableSlaveSelect(SPI2_CH1);

    // Wait till MSLS disabled
    while((XMC_SPI_CH_GetStatusFlag(SPI2_CH1) & XMC_SPI_CH_STATUS_FLAG_MSLS) == 1U); 


    XMC_GPIO_SetOutputHigh(SOFT_CS);
}

I'm also attaching a picture of both SPI slave select signals. The first channel is the hardware slave select and second channel is the GPIO slave select.

Show Less

Hi to all,

can any one suggest me that......

is there any infineon xmc1000 series with connectivity of can protocol..

My requirements : The chip should be cost 1 $-2$ maximum
it should be Auto grid ...
connectivity : CAN ,usart,i2c

i had searched many chips from infineon of xmc1000 ,but i can't find the product as per my requirement.. please find the attachment of excel sheet of Xmc1000 series concluded by my
research.

please let me know if any suggestions regarding this issue.thanks for your reply Show Less