Hi,
I have configured XMC 4100 as SPI master,which is interfaced to SPI EEPROM. I want to independently control the chip select irrespective of frame length, So I kept Frame-Length=64, and Wordlength = 8; and I am using FIFO mechanism. My intended operation is:
1->Chip Select low.
2->Transfer bytes( Not fixed).
3->CS High.

How should I configure to achieve this? Show Less

Hi all,

Does anyone has information when there will be available a APP to implement a SPI slave on DAVE 4?

It exists on DAVE 3 (SPI003). I will implement it if is not available, but before spending time on it I would like to know if it exists or is there any plan to add it?


Best regards,
Filipe Show Less

Is there any way to start the communication via the USICs at the same time.
I would like to load the TX FIFO with the data to send and then have the output of a timer start the transmission at the same time.
I need to read the data from 2 sensors on two I2C buses at the same time to be able to compare the values.
Can the USIC enable be controlled from the output of a CCU8 unit? Show Less

Hi,
I am working on 4100 SSC module, I am using SPI for interfacing EEPROM.which flag we should check for successful transmission of Frame and which flag for Receive, I read the 4100 reference manual they have mentioned Transmit Shift Flag, Recieve Indication Flag & Alternate Receive Indication flag, So can we say after successful transmission Transmit Shift flag gets enabled and for Recieve, Receive Indication flag gets set?
Kindly help me out.

Regards,
Irfan Show Less

Hi,

here I have an 16bit Timer.
Now to my question, is it possible to make a software interrupt in the function "CCU40_0_IRQHandler"? And have you an idea or have you an example without Apps (e.g. CMSIS) ?
The idea is an second timer wich is synchron to the CCU40_0_IRQHandler...

XMC_CCU4_SLICE_COMPARE_CONFIG_t timer_config_ccu40 = {
		.timer_mode = XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA,
		.monoshot = XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT,
		.prescaler_initval = 0, };


	/** 16 Bit Timer **/

	XMC_CCU4_Init(CCU40, XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR);
	XMC_CCU4_SLICE_CompareInit(CCU40_CC40, &timer_config_ccu40);
	XMC_CCU4_SLICE_SetTimerPeriodMatch(CCU40_CC40, 0x2328);

	XMC_CCU4_SLICE_EnableEvent(CCU40_CC40, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH);
	XMC_CCU4_SLICE_SetInterruptNode(CCU40_CC40, XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH, 0);
	NVIC_SetPriority(CCU40_0_IRQn, 2);
	NVIC_EnableIRQ(CCU40_0_IRQn);
	XMC_CCU4_StartPrescaler(CCU40);
	XMC_CCU4_EnableShadowTransfer(CCU40, XMC_CCU4_SHADOW_TRANSFER_SLICE_0);

	XMC_CCU4_EnableClock(CCU40, 0);
	XMC_CCU4_SLICE_StartTimer(CCU40_CC40);


void CCU40_0_IRQHandler(void)
{
	#if 0
	if((CCU40_CC40->INTS)&0x00000001)
	{

	}
	#endif

-->>>>  (Software)  Interrupt ??? <<<<<--

	CCU40_CC40->SWR |= 0x00000001;
}

Thanks... Show Less

Hello,

Is there available some more information about XMC retention memory? More documentation, some example, access times... I am observing that writing access has variable time. What could be delaying write access?

rum Show Less

Hi,

Now I'm already working for a while with the XMC and would like to set the chip select line(s) in the SPI module.
The set of the CS lines I have already found out.
For a better understanding of my program: I (we) write to all needed hardware XMC modules classes where methods for configuration and actions are provided.

The SPI-Module is configured as:
- Mode: SPI001_STANDARD_FULLDUPLEX;
- BaudRate = 40000
- FrameLen: 16
- WordLen: 16
- HBMode: SPI001_MSB
- ClkPol: SPI001_CLK_POL1
- ClkPh: SPI001_CLK_PHASE0v
- LeadTrailDela: SPI001_ONE_SCLK_PERIOD
- NextFrameDelay: SPI001_ONE_SCLK_PERIOD;
- Transmit/Receive FIFO ... Size: 16 Bit; Trigger limit: 1
- CSPol: inverted (Active-Low)


My Idea is to change the CS-Pattern before I want to transmit a message.
This means:

if FIFO is not full
    If CS-Pattern has changed
        wait until fifo is emty
        change cs patterm
    send message

In the method for sending the SPI messages, I have to select the CS line following code:

// if chip-select pattern has changed since last run
	// first part: set the SELO Register to 0x00
	USICRegs->PCR_SSCMode &= ~USIC_CH_PCR_SSCMode_SELO_Msk;
	// second part: write the cspattern into SELO-Register
	USICRegs->PCR_SSCMode |= (cspattern << USIC_CH_PCR_SSCMode_SELO_Pos)
		& USIC_CH_PCR_SSCMode_SELO_Msk;
	// store current cs pattern for next run

Now i found out ...
SPI001_TRANS_SHIFT_IND_FLAG --> TSIF (transmit event happened)
SPI001_FIFO_STD_TRANSMIT_BUF_FLAG --> STBI (transmit buffer event happened)
SPI001_FIFO_TRANSMIT_BUF_ERR_FLAG --> TBERI (transmit buffer error happened)

And i wanted to solve my problem as followed. Meanwhile, we do not consider: "if FIFO is not full"

while((SPI001_GetFlagStatus(p->handle, SPI001_TRANS_SHIFT_IND_FLAG))!=SPI001_SET);	
//alternatively also: while((SPI001_GetFlagStatus(p->handle, SPI001_FIFO_STD_TRANSMIT_BUF_FLAG))!=SPI001_SET);
SPI001_ClearFlag(p->handle,SPI001_TRANS_SHIFT_IND_FLAG);
//alternatively also: SPI001_ClearFlag(p->handle,SPI001_FIFO_STD_TRANSMIT_BUF_FLAG);

EnableStartOfFrame((*p->handle)); 		// removing/adding did non bring a improvement
SPI001_WriteData(p->handle, &data, SPI001_STANDARD); // send Data
EnableEndOfFrame((*p->handle)); 		// removing/adding did non bring a improvement

==> At sending more messages the CS-Pattern get changed immediately (all messages gets sended with configuration for last message) and the messages get transferred in FIFO Buffer.
When a sufficient number of messages (>~20), the CS pattern get changed sometime ...


I also observed the TSIF, STBI and TBERI
TSIF ... every run one
STBI ... every two one except the first run (why)
TBERI ... every run one

Now my question to you .... how can I reach my "wish" to change the CD Pattern before sending the message / every message.
But wait directly after sending the message up to the time when the FIFO Buffer is empty is no option for me.

Best regards and Thank for your help!
Gerald Show Less

I am attempting to perform the calibration steps outlined in errata ADC_AI.004 based on my interpretation of the wording, but when I add it to the code, my subsequent PWM triggered ADC sampling following the calibration no longer executes. In particular, the call to write BRSMR.LDEV prevents subsequent calls to the ADC result event handler. I am not otherwise using LDEV in my code.

	/**
	 * Perform calibration to compensate for bug ADC_AI.004
	 */
	SET_BIT( pVADCGlobal->GLOBCFG, VADC_GLOBCFG_SUCAL_Pos);
	while (RD_REG( pSHS->SHSCFG, SHS_SHSCFG_STATE_Msk, SHS_SHSCFG_STATE_Pos ) != 0)
	{
		*(uint32_t *)0x480340E0 = 0x00008000;
		*(uint32_t *)0x480340E4 = 0x00008000;
	}
	for (i=0; i<1; i++)
	{
		for (j=0; j<9; j++)
		{
			pVADCGlobal->BRSSEL[0] = 0x01;
			SET_BIT( pVADCGlobal->BRSMR, VADC_BRSMR_LDEV_Pos );
			while (RD_REG( pVADCGlobal->GLOBEFLAG, VADC_GLOBEFLAG_REVGLB_Msk, VADC_GLOBEFLAG_REVGLB_Pos ) != 1);
			ADCResult = pVADCGlobal->GLOBRES;
		}
		*(uint32_t *)0x480340E0 = 0x00008000;
		*(uint32_t *)0x480340E4 = 0x00008000;
	}

At this stage in the code, I have not yet enabled the result event or the IRQ.

I think that the errata needs to be updated with more details and should include some source code along with any cleanup code that is required. Show Less

Hello,

I am using XMC1302-T038X0064 MCU.
How can I find out which stepping I have. Marking only tells me 064A.

Is there an errata for the AB stepping? The AA stepping still has a lot of bugs. Show Less

For XMC4500, is read or write of uint32_t, uint6_t or uint8_t type of data atomic? how about accessing element of a struct of mixed data types, is the access atomic?

struct status_t {
uint8_t status1;
uint16_t satus2;
} Show Less