Hey guys,

we want to use the XMC4400-Board + MotorControl-Board (MOT_GPDLV_V2) + DAVE3 to control a brushless BLDC-Motor with 3 hall-sensors.

For our application we have to use the motor as an active break, which means that we have to use a special control algorithm.

Does anybody have any experience with BLDC-control or example code?

We already tried to use the BLDCBCH03-App and change the generated code, but we couldn't understand the algorithm.

We suppose that the used implementation is based on peripheral modules...

We hope you can help us
best regards Show Less

we are being evaluated for the passage of our platforms Spansion 16FX family in infineon in xmc4500 family suggested by EBV italy and
against our will see that it is released implementer configuration Ebu in case you have to do with the type of sram memories, nor, external
bus interface display (with integrated controller) I would like to stimulate the technical department to release an application note that
can guide us in a simple configuration of the device (in xmc library EBU config file) for us is essential to have a configuration suggested
by infineon is strange as I read in the forum that is not planned for you should be the work of a day we need your kind support if we start
working together for us would be a pleasure Show Less

Hi,

What is the IRQ line for SR3 in CCU8?

I have found these settings in XMC1300.h

  CCU40_0_IRQn        =  21,   /*!< CCU40 SR0 Interrupt                      */
  CCU40_1_IRQn        =  22,   /*!< CCU40 SR1 Interrupt                      */
  CCU40_2_IRQn        =  23,   /*!< CCU40 SR2 Interrupt                      */
  CCU40_3_IRQn        =  24,   /*!< CCU40 SR3 Interrupt                      */
  
  CCU80_0_IRQn        =  25,   /*!< CCU80 SR0 Interrupt                      */
  CCU80_1_IRQn        =  26,   /*!< CCU80 SR1 Interrupt                      */
  

Why no CCU80_3_IRQn? The XMC1300 reference manual says, it has SR0-SR3 service lines.

So how to change in my code (I have to port it to CCU8)

    NVIC_SetPriority(CCU40_3_IRQn, 3);  
    NVIC_EnableIRQ(CCU40_3_IRQn);   

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Hi,

My name is chethan kumar recently i brought XMC1400 Boot Kit for bldc motor control application using PMSM_FOC app. This app only available for XMC1300 series,
so did below mentioned procedure
1. i configure and generate the FOC code as per our BLDC motor in XMC1300 series created project.
2. Generated library files pasted to XMC1400 series project.
3. changed the pin mapping.
Here i got error in PMSM_FOC_ADCconfig, it is only for XMC13.
I don't know this is right or wrong because i am new to infineon controllers, kindly suggest me how to configure in XMC1400 series.

Regards,
Chethan kumar Show Less

This code trying to write to an reserved address on XMC1300.
Write to the ADDR generates hard fault but it is called continiusly, why?

At this point called hard fault but the the interrupt returned exactly to the same address, and after hard fault called again and again.
Why returns the interrupt to 0x10001196 instead of 0x10001198 (which is the next address)
10001196: str r2, [r3, #0]

11         int* p = ADDR;
1000118e:   ldr r3, [pc, #12]       ; (0x1000119c 
)
10001190:   str r3, [r7, #4]
13         *p = 1;
10001192:   ldr r3, [r7, #4]
10001194:   movs r2, #1
10001196:   str r2, [r3, #0]
15         while(1);
10001198:   b.n 0x10001198 

#include 

#include "XMC1300.h"
#include "GPIO.h"

#define ADDR 0x40000800

int main(void)
{

 int* p = ADDR;
 
 *p = 1;
 
 while(1);
}

void HardFault_Handler()
{
}

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Hi folks,

I'm currently working with an XMC4500 Relax Lite Kit using DAVE v4.1.4.
To investigate the timing behavior I have written a small measurement framework that causes an interrupt after 1, 2, 3, ..., n cycles until the program subject to measurement has completed.

Main measurement framework structure:
1. initialize hardware (enable FPU)
2. initialize measurement storage (DSRAM2)
3. invalidate PMU instruction buffer
4. disable sysclock
5. setup new systick reload value
6. reset current systick value
7. enable sysclock, systick exception, setup fCPU as clock source
8. execute measurement code
9. disable syslock

SysTick_Hander structure:
1. disable systick timer
2. update measurement sample (store pc of interrupted instruction to DSRAM2)
3. update systick reload value = last value + 1
4. return to measurement framework step 3.

So, in principle I can observe the progression of the control-flow until we have reached step 9 of the measurement framework.


Currently, I'm facing an unexpected behavior when in comes to the execution of code from cached and uncached PMU FLASH memory.
Apparently, code being executed from cached PMU FLASH appears to be executed much slower.

The piece of code subject to measurement is the following (i.e., 10 iterations of "loop"):

    movs r7, #10
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop

loop:
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    sub r7, #1
    cmp r7, #0
    bne loop

    nop
    nop
    nop
    nop
    bx lr

Using the measurement framework I observe the following execution times (in cycles):

a) PREF_PCON = 0x0
FLASH0_FCPON = 0x3 (=> 3 read wait states)
Executing from PMU FLASH cached => 1809 cycles
Executing from PMU FLASH uncached => 681 cycles

b) PREF_PCON = 0x1 (=> PMU instruction buffer bypassed)
FLASH0_FCPON = 0x3 (=> 3 read wait states)
Executing from PMU FLASH cached => 681 cycles
Executing from PMU FLASH uncached => 681 cycles


How can it be that the code when being executed from PMU FLASH cached is approximately 3 times slower than when being executed from PMU FLASH uncached memory?
I have also tried to only measure the difference between the systick timer before and after the execution (i.e., no interrupts while executing the loop) with the same results.

Does anyone have a clue? What am I missing?


P.S.: I would have uploaded the full startup code, but apparently I cannot upload .S files to the forum. Show Less

Micron/Infineon Solutions
Select Micron DRAM as well as NAND and NOR flash solutions are validated on Infineon’s XMC™ microcontrollers. Minimize time spent searching for memory compatibility with XMC products.


Download the Micron/Infineon Compatibility Guide to see Micron memory solutions that support Infineon interfaces:
https://www.micron.com/~/media/documents/products/other-documents/micron_infineon_compatability_guide.pdf?la=en

More information on Micron Valued Partner Program:
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Hi,

I found these two bits in the datasheet of the XMC1100: SP0 and SP1. I found them in the chapter VADC module, SHS0 registers. They are take place in the SHSCFG register. I wrote a program, which uses five input channels. I set continuous conversion.
The datasheet says about these two bits:

Sample Pending on Group x
0: No sample pending
1: Group x has finished the sample phase

I debug the program. These two bits did not change, these were always 0.

How are these bits work? Could somebody tell me?

Rjani Show Less