XMC™ Forum Discussions
XMC™
Hi,I have an XMC 1404 connected to a SD card via the SPI bus.I'm using the standard FATFS App with the default main and configurations as described in...
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Hi,
I have an XMC 1404 connected to a SD card via the SPI bus.
I'm using the standard FATFS App with the default main and configurations as described in the FATFS help documentation.
I've upgraded the SDMMC_BLOCK app from version "4.0.22" to version "4.3.22" and the code no longer compiles.
the lines:
have been adde to "sdmmc_block_conf.c".
If I remove them then the code compiles as normal, however each time I generate the code they get added back in again.
What am I doing wrong?
Cheers,
Nick Show Less
I have an XMC 1404 connected to a SD card via the SPI bus.
I'm using the standard FATFS App with the default main and configurations as described in the FATFS help documentation.
I've upgraded the SDMMC_BLOCK app from version "4.0.22" to version "4.3.22" and the code no longer compiles.
the lines:
#if (UC_SERIES != XMC45)
XMC_SDMMC_SetWriteProtectionSource(XMC_SDMMC, XMC_SDMMC_WP_SOURCE_SW);
XMC_SDMMC_SetWriteProtectionStatus(XMC_SDMMC, XMC_SDMMC_WP_STATUS_NO_WRITE_PROTECTION);
#endif
have been adde to "sdmmc_block_conf.c".
If I remove them then the code compiles as normal, however each time I generate the code they get added back in again.
What am I doing wrong?
Cheers,
Nick Show Less
XMC™
hi,i have a project with a xmc4400 which don't use a hibernate section and rtx_xtall. At start-up the system stay infinite loop inside at function XMC...
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hi,
i have a project with a xmc4400 which don't use a hibernate section and rtx_xtall. At start-up the system stay infinite loop inside at function XMC_SCU_HIB_SetRtcClockSource. The register MCU_GENERAL->MIRRSTS is not real!!
My Personal patch is check bit fixed inside of this register for determinate if is real or not. This is my patch:
/* API to select fRTC */
void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source)
{
/*PATCH */
if ((SCU_GENERAL->MIRRSTS & 0x00000010) != 0)
return;
/* Wait until the update of HDCR register in hibernate domain is completed */
while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
}
Why do I have to do this?
I made some mistakes in the initialization?
Dave Version: 4.2.2
I await comments thanks. Show Less
i have a project with a xmc4400 which don't use a hibernate section and rtx_xtall. At start-up the system stay infinite loop inside at function XMC_SCU_HIB_SetRtcClockSource. The register MCU_GENERAL->MIRRSTS is not real!!
My Personal patch is check bit fixed inside of this register for determinate if is real or not. This is my patch:
/* API to select fRTC */
void XMC_SCU_HIB_SetRtcClockSource(const XMC_SCU_HIB_RTCCLKSRC_t source)
{
/*PATCH */
if ((SCU_GENERAL->MIRRSTS & 0x00000010) != 0)
return;
/* Wait until the update of HDCR register in hibernate domain is completed */
while((SCU_GENERAL->MIRRSTS) & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
}
Why do I have to do this?
I made some mistakes in the initialization?
Dave Version: 4.2.2
I await comments thanks. Show Less
XMC™
Hello,working on a small bootloader project which parses an incoming .HEX file on UART and puts it to flash.The incoming data is received by UART RX i...
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Hello,
working on a small bootloader project which parses an incoming .HEX file on UART and puts it to flash.
The incoming data is received by UART RX interrupt (USIC0_0_IRQHandler), which itself is put to RAM. The vector table is still located in flash, which will probably prevent any ISR call while erasing/writing flash. Or isn't this necessary at all?
1. The vector offset register (VTOR) is present as PPB->VTOR and SCB->VTOR. Which one I am supposed to use?
2. I know that the vector table must be placed in flash after start-up, because the reset handler cannot be run when placed in RAM. So I basically need to put the vector table in beginning of flash as well as RAM. How do I tell the linker script to do so?
Best regards,
Ernie Show Less
working on a small bootloader project which parses an incoming .HEX file on UART and puts it to flash.
The incoming data is received by UART RX interrupt (USIC0_0_IRQHandler), which itself is put to RAM. The vector table is still located in flash, which will probably prevent any ISR call while erasing/writing flash. Or isn't this necessary at all?
1. The vector offset register (VTOR) is present as PPB->VTOR and SCB->VTOR. Which one I am supposed to use?
2. I know that the vector table must be placed in flash after start-up, because the reset handler cannot be run when placed in RAM. So I basically need to put the vector table in beginning of flash as well as RAM. How do I tell the linker script to do so?
Best regards,
Ernie Show Less
XMC™
hi,i am trying WATCHDOG App in DAVE and want to connect service indication pulse signal to DIGITAL IO App. In HW signal connection, i cannot find DIGI...
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hi,
i am trying WATCHDOG App in DAVE and want to connect service indication pulse signal to DIGITAL IO App. In HW signal connection, i cannot find DIGITAL IO when want to assign connect service indication pulse signal to Digital IO. do i miss some steps ?
Best Regards,
Teman XMC[HTML][/HTML] Show Less
i am trying WATCHDOG App in DAVE and want to connect service indication pulse signal to DIGITAL IO App. In HW signal connection, i cannot find DIGITAL IO when want to assign connect service indication pulse signal to Digital IO. do i miss some steps ?
Best Regards,
Teman XMC[HTML][/HTML] Show Less
XMC™
I have a XMC4500 on a board designed by ourselves. I can download a program and it runs correctly, but if I run it with the debugger the program runs ...
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I have a XMC4500 on a board designed by ourselves. I can download a program and it runs correctly, but if I run it with the debugger the program runs correctly for about 20ms and then ends up in an endless loop in the boot ROM.
I am using RTX and the jump to the boot ROM occurs while in the idle loop.
My questions:
1. How is it possible to end up in the boot ROM from a running program? (It cannot be an invalid pointer in the idle loop)
2. Why does it not just restart, the hardware configuration is correct the first time.
3. What effect can the debugger (Keil ULINKpro) be having to cause this? Show Less
I am using RTX and the jump to the boot ROM occurs while in the idle loop.
My questions:
1. How is it possible to end up in the boot ROM from a running program? (It cannot be an invalid pointer in the idle loop)
2. Why does it not just restart, the hardware configuration is correct the first time.
3. What effect can the debugger (Keil ULINKpro) be having to cause this? Show Less
XMC™
Hello, I need to keep the XMC PWM synchronized with an external synch signal.PWM frequency is nominally 16 times the external synch signal, but since ...
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Hello, I need to keep the XMC PWM synchronized with an external synch signal.
PWM frequency is nominally 16 times the external synch signal, but since it comes from a different clock it has some error.
I would like to PLL the XMC PWM, so I need to update the PWM period from time to time, without stopping it.
DAVE has a PWM_SVM_SetPWMFrequency but it is clearly stated it only works when PMW is stopped.
Is there any particular reason for this?
How can it be done?
Thanks.
Alberto Show Less
PWM frequency is nominally 16 times the external synch signal, but since it comes from a different clock it has some error.
I would like to PLL the XMC PWM, so I need to update the PWM period from time to time, without stopping it.
DAVE has a PWM_SVM_SetPWMFrequency but it is clearly stated it only works when PMW is stopped.
Is there any particular reason for this?
How can it be done?
Thanks.
Alberto Show Less
XMC™
Hello,with SPI_Master_App--> FullDuplex(lib up to date, DMA or Interrupt is the same limit), I see a baudrate limit @24MHz with Dave 4.4.2. Has anybod...
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Hello,
with SPI_Master_App--> FullDuplex(lib up to date, DMA or Interrupt is the same limit), I see a baudrate limit @24MHz with Dave 4.4.2. Has anybody an idea, why I can not increase the baudrate?
Regards,
Peter Show Less
with SPI_Master_App--> FullDuplex(lib up to date, DMA or Interrupt is the same limit), I see a baudrate limit @24MHz with Dave 4.4.2. Has anybody an idea, why I can not increase the baudrate?
Regards,
Peter Show Less
XMC™
Hi, i'm facing the problem with this board. I have connected XMC1100 Kit(for Arduino) to W5500 Ehernet Board(1471-1413-ND) via SPI. When communication...
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Hi, i'm facing the problem with this board. I have connected XMC1100 Kit(for Arduino) to W5500 Ehernet Board(1471-1413-ND) via SPI. When communication starts, all is so slow. I mean data transfer is slower than i expected. I seems SPI bus has a lot of errors or something. When i touch osciloscope probe to CLK pin then communication stops. I see in my debug console just ,,disconnected,, and board needs reset to start communication again. When i switched to Arduino UNO(Circuit stayed the same. Sketch stayed the same. Web Server sketch from Ethernet 2 library.) its works perfectly. Datasheet says: fully compatible with Arduino. So please where is the problem ? Thanks
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XMC™
Hi Infineon Community and Infineon StaffWe have a well working application with the Infineon XMC4500 Step AC for about one year now. Because our appli...
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Hi Infineon Community and Infineon Staff
We have a well working application with the Infineon XMC4500 Step AC for about one year now.
Because our application is very memory intensive we use the EBU to have external RAM and also we have an external NAND Flash we use with a Filesystem.
We also use the Ethernet Port and USB Host.
Besides this we use 2 USIC Channels in SPI Mode and 3 USIC Channels in UART Mode, the RTC and 3 CAN Nodes with various Message Objects.
For Memory Transfer to the NAND Flash and Datatransfer over SPI we use the GPDMA of the XMC4500.
We now want to port our software Project onto the XMC4700 Step AA because it has more internal RAM and more internal FLASH.
We checked two main differences between XMC500 and XMC4700:
1. Memory Map of internal RAM is different and not compatible (PSRAM and DSRAM), so we changed the Linker Configuration
2. CAN Initialisation is different.
With this two changes the software which works perfectly on the XMC4500 step AC works also on the XMC4500.
But there is one difference:
Sporadically we get Bus Error Traps during DMA Transfers and we can't find the reason for it.
There are no such traps on the XMC4500 with the same Software. We checked for stack overflows and overwriting array boundaries but there is no such problem.
The clock System is configured like on the XMC4500 with fpll = 120 MHz and fsys = 120 MHz. The Clock Konfiguration is checked and is the same.
The EBU Timing is also verified on both CPUs.
Is there any other difference in the two CPUs I don't know about ?
Is there anybody from Infineon staff who can help me with this issue ?
Thanks for your help
Ingo Show Less
We have a well working application with the Infineon XMC4500 Step AC for about one year now.
Because our application is very memory intensive we use the EBU to have external RAM and also we have an external NAND Flash we use with a Filesystem.
We also use the Ethernet Port and USB Host.
Besides this we use 2 USIC Channels in SPI Mode and 3 USIC Channels in UART Mode, the RTC and 3 CAN Nodes with various Message Objects.
For Memory Transfer to the NAND Flash and Datatransfer over SPI we use the GPDMA of the XMC4500.
We now want to port our software Project onto the XMC4700 Step AA because it has more internal RAM and more internal FLASH.
We checked two main differences between XMC500 and XMC4700:
1. Memory Map of internal RAM is different and not compatible (PSRAM and DSRAM), so we changed the Linker Configuration
2. CAN Initialisation is different.
With this two changes the software which works perfectly on the XMC4500 step AC works also on the XMC4500.
But there is one difference:
Sporadically we get Bus Error Traps during DMA Transfers and we can't find the reason for it.
There are no such traps on the XMC4500 with the same Software. We checked for stack overflows and overwriting array boundaries but there is no such problem.
The clock System is configured like on the XMC4500 with fpll = 120 MHz and fsys = 120 MHz. The Clock Konfiguration is checked and is the same.
The EBU Timing is also verified on both CPUs.
Is there any other difference in the two CPUs I don't know about ?
Is there anybody from Infineon staff who can help me with this issue ?
Thanks for your help
Ingo Show Less
XMC™
Hello, I am working on XMC4500 USB in VCOM mode, the device is detected as USB serial device on Windows 10 platform and i am able to communicate.The p...
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Hello,
I am working on XMC4500 USB in VCOM mode, the device is detected as USB serial device on Windows 10 platform and i am able to communicate.
The problem is the same device is not detected in windows 7 platform, it is detected as unknown device. please any body give solution for this, or provide me corresponding USB drivers for windows 7 platform.
Best Regards,
Srikanth L. Show Less
I am working on XMC4500 USB in VCOM mode, the device is detected as USB serial device on Windows 10 platform and i am able to communicate.
The problem is the same device is not detected in windows 7 platform, it is detected as unknown device. please any body give solution for this, or provide me corresponding USB drivers for windows 7 platform.
Best Regards,
Srikanth L. Show Less
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