Hello,
I tried to get a SPI communication and I found this excampler here.
But there is no "Chip-Select" Signal at P0.9.
Thank you for any help!
Bernd
void initSPI(void) {
/* SPI Master initialization */
uint32_t spiFdrStep = 0, spiFsclk = 500000;//500000;
uint8_t spiBrgPdiv = 0;
/* if PPPEN = 0
* fsclk = fsys x STEP/1024 x 1/2 x 1/PDIV+1
*
* if PPPEN = 1
* fsclk = fsys x 1/2 x STEP/1024 x 1/2 x 1/PDIV+1
*/
/* Calculate settings for desired fsclk, PPPEN = 1 */
while(1) {
spiFdrStep = (spiFsclk * 1024 * 2 * 2 * (spiBrgPdiv+1)) / SystemCoreClock;
if(!((0 <= spiFdrStep) && (spiFdrStep < 1024))) {
spiBrgPdiv++;
} else {
break;
}
}
/* Disable clock gating to USIC0 */
SCU_GENERAL->PASSWD = 0x000000C0UL; /* disable bit protection */
SCU_CLK->CGATCLR0 |= SCU_CLK_CGATCLR0_USIC0_Msk;
SCU_GENERAL->PASSWD = 0x000000C3UL; /* enable bit protection */
// Enable the module kernel clock and the module functionality
USIC0_CH0->KSCFG |= (1ul << USIC_CH_KSCFG_MODEN_Pos) | (1ul << USIC_CH_KSCFG_BPMODEN_Pos);
// Configuration of Channel Control Register, set USIC to SSC.SPI
USIC0_CH0->CCR |= (SPI_MODE << USIC_CH_CCR_MODE_Pos);
// Configure Fractional Divider Register
USIC0_CH0->FDR |= (spiFdrStep << USIC_CH_FDR_STEP_Pos) | (NORMAL_DIVIDER_MODE << USIC_CH_FDR_DM_Pos);
// Configure Baud Rate Generator Register */
USIC0_CH0->BRG |= (1ul << USIC_CH_BRG_PPPEN_Pos)
| (spiBrgPdiv << USIC_CH_BRG_PDIV_Pos)
| (0ul << USIC_CH_BRG_PCTQ_Pos)
| (9ul << USIC_CH_BRG_DCTQ_Pos);
USIC0_CH0->PCR_SSCMode |= (1ul << USIC_CH_PCR_SSCMode_MSLSEN_Pos) // Enables/disables the generation of the master slave select signal
| (1ul << USIC_CH_PCR_SSCMode_SELINV_Pos) // Active low for CS
| (1ul << USIC_CH_PCR_SSCMode_SELCTR_Pos) // Direct select
| (PORT0_9 << USIC_CH_PCR_SSCMode_SELO_Pos)// Activate SELO0
| (1ul << USIC_CH_PCR_SSCMode_MCLK_Pos); // Master Clock Enable
// Configure Shift Control Register
USIC0_CH0->SCTR |= (1ul << USIC_CH_SCTR_SDIR_Pos) // Shift out MSB first
| (0ul << USIC_CH_SCTR_DSM_Pos) // Data Shift Mode
| (SPI_MODE << USIC_CH_SCTR_TRM_Pos) // Transmission Mode
| (7ul << USIC_CH_SCTR_FLE_Pos) // Frame Length
| (7ul << USIC_CH_SCTR_WLE_Pos); // Word Length
// Configure Transmission Control Status
USIC0_CH0->TCSR |= (0ul << USIC_CH_TCSR_FLEMD_Pos) // FLE Mode
| (0ul << USIC_CH_TCSR_WLEMD_Pos) // WLE Mode
| (0ul << USIC_CH_TCSR_SELMD_Pos) // Select Mode
| (0ul << USIC_CH_TCSR_SOF_Pos) // Start Of Frame
| (0ul << USIC_CH_TCSR_EOF_Pos) // End Of Frame
| (0ul << USIC_CH_TCSR_TDV_Pos) // Transmit Data Valid
| (1ul << USIC_CH_TCSR_TDSSM_Pos) // TBUF Data Single Shot Mode
| (1ul << USIC_CH_TCSR_TDEN_Pos); // TBUF Data Enable
USIC0_CH0->TBCTR &= ~(USIC_CH_TBCTR_SIZE_Msk | USIC_CH_TBCTR_DPTR_Msk);
USIC0_CH0->TBCTR |= ((0x05 << USIC_CH_TBCTR_SIZE_Pos)|(0x00 << USIC_CH_TBCTR_DPTR_Pos));
// Set P0.15 as Input, MISO
P0_15_set_mode(INPUT);
//Select DX0B
USIC0_CH0->DX0CR |= (1ul << USIC_CH_DX0CR_DSEL_Pos) | (1ul << USIC_CH_DX0CR_INSW_Pos);
// Set P0.14 as Onput, MOSI
P0_14_set_mode(OUTPUT_PP_AF6);
// Set P0.7 as Output, SCLK
P0_7_set_mode(OUTPUT_PP_AF6);
// Set P0.9 as Output, SELECT
P0_9_set_mode(OUTPUT_PP_AF6);
}
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