The use case:
I want to timestamp edges for 8 different input signals.
The timestamps should have 64 bit resolution.

The problem:
The CCU4/8 have 16 bit resolution, which is insufficient. Timer concatenation can't be used as some of the signals share CCU module (using different slices).
As far as I can tell, it is not possible to generate an interrupt when timer wraps around while in Capture mode.

The question:
How do I work around this problem? Show Less

Hi,

As per the Application Note AP32289 the POSIF module can be set to only to any one mode from the following:

- 00B: Hall Sensor Mode
- 01B: Quadrature Decoder Mode
- 10B: Stand-alone Multi-Channel Mode
- 11B: Stand-alone Multi-Channel & Quadrature Decoder Mode

Does that mean only the hall sensor outputs or the encoder outputs be monitored by the POSIF module in the XMC1300 series but not the outputs from both the sensors at the same time? Show Less

Hello everyone,
I tried to get DC clock synchronization working on the XMC4800 EtherCAT kit -- both with the current "XMC4800 Relax EtherCat Slave SSC" (http://www.infineon.com/dgdl/Infineon-XMC4800_Relax_EtherCat_Slave_SSC-GS-v01_00-EN.ZIP?fileId=5546d462525dbac401525e3a97391261) as well as the "HOT_XMC48_ECAT_GettingStarted" from http://www.infineonforums.com/threads/3552-XMC4800_HOT-EtherCAT-Getting-Started-with-XMC4800-relax-kit .
I basically set AL_EVENT_ENABLED, DC_SUPPORTED, and ECAT_TIMER_INT in the SSC tool to '1'. however, looking into the stack code, I saw that actually everything looking like configuring the SYNC0 ISR actually does nothing -- like that part is just not implemented (c.f. ECAT0_Init_SYNC0_INT() in ECAT0.c). What am I actually missing?
Thanks very much for any hint!
BR, Chris Show Less

What does "HW controlled shift data input" within the USIC Interconnects description stand for?

Does this mean, this pin can either be input OR output?

Thank you! Show Less

Hello,

I am not able to start up the Ethercat Slave device (Relaxkit), when I enable DC-Sync Mode in Ethercat Master Configuration!

I created the EtherCAT Slave application with the newest tutorial and versions of DAVE and Ethercat Slave Source Stack Tool.
The tutorial ist very good, so there was no problem to bring up the slave demo on the Relax Kit.

When I run the Ethercat in FreeRun/SM-Sync Mode, everything is fine, but when changing to DC-Sync, the slaves fails in State Transition from SAVE-OP to OPERATIONAL.
I debugged already a while, but I am not able to find the reason for this behaviour!

Any Ideas?

Many Thanks

Richard Show Less

Hello,

we are evaluating XMC4800 for an ETHERCAT solution.
Beside ETHERCAT we need external bus Interface (EBU) for accessing FPGA.
16 Bit Adress/Data multiplexed

According to the Port I/O function table ( Datasheet 2.2.2.1)we have not found a valid solution for the pin assignment.

We have conflicts with PINs P0.4, P0.5 and P0.6
They are used for both EBU and ECAT and do not have any alternative mapping.

Any solution or is it impossible at all to use XMC4800 with ECAT and EBU ?

Many Thanks Show Less

Hi,

i found a Dave-App for Space Vector Modulation on XMC 4500 microcontrollers. Will the App get updated so I can also use it on the XMC 4700 in the future?

Regards,

Julius Show Less

Dear all,

At the moment I am playing with the XMC4400 and I have the timer slices 0, 1 and 3 of Timer Module 0 running

according to example 3 of AP32288: CU8 initialization for 3 phase motor drive.

Everying is working as expected.

What I want to do now, is to introduce a phase shift between the carriers by changing the initial value of the Timer as following at the beguining of the main:

XMC_CCU8_SLICE_SetTimerValue(SLICE00_PTR, 200U);
XMC_CCU8_SLICE_SetTimerValue(SLICE01_PTR, 500U);
XMC_CCU8_SLICE_SetTimerValue(SLICE03_PTR, 1000U);

/* Set period match value of the timer module1 */
XMC_CCU8_SLICE_SetTimerPeriodMatch(SLICE00_PTR, 1499U);
XMC_CCU8_SLICE_SetTimerPeriodMatch(SLICE01_PTR, 1499U);
XMC_CCU8_SLICE_SetTimerPeriodMatch(SLICE03_PTR, 1499U);

for some reason the Period is set correctly but not the Timer value, and when I read it, after having set the value, I get the value 0:

A = XMC_CCU8_SLICE_GetTimerValue(SLICE00_PTR);

Can anyone help me with this ? How do I set the initial Timer value that I want correnctly in order to optain the desired phase-shift?

Thank you very much! 🙂 Show Less

Dear all,

i have trouble to start a Linked List DMA Transfer triggered by an ADC event.
I´m using the XMC4500 hexagon board v2 with Dave 4 and the XMClib.

My Problem:
I´ve got a periodic synchronized ADC conversion (G0CH0, G0CH1 with G1CH0, G1CH1). The result event (of G0CH1) should trigger the DMA Transfer.
As there are two ADC Groups and therefore different group result registers, i would like to use a DMA Transfer with a linked list for the source/destination adress.

Here is my code:

uint16_t verify_ADC_Result1[2],verify_ADC_Result2[2];
XMC_DMA_LLI_t liste1, liste2;

void DmaInit(void)
{
	XMC_DMA_LLI_t liste1 =
	{
		.src_addr 				= (uint32_t)&VADC_G0->RES[0],
		.dst_addr 				= (uint32_t)&verify_ADC_Result1[0],
		.llp					        = &liste2,
		.block_size				= 8,
		.dst_transfer_width 	           = XMC_DMA_CH_TRANSFER_WIDTH_16,
		.src_transfer_width             = XMC_DMA_CH_TRANSFER_WIDTH_16,
		.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		.dst_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		.src_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		.enable_dst_linked_list    = true,
		.enable_src_linked_list    = true,
		.transfer_flow 			= XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
		.enable_src_gather		= true,
		.enable_dst_scatter		= false,
	};
	XMC_DMA_LLI_t liste2 =
	{
		.enable_interrupt		        = true,
		.src_addr 				= (uint32_t)&VADC_G1->RES[0],
		.dst_addr 				= (uint32_t)&verify_ADC_Result2[0],
		.llp					        = 0,
		.block_size				= 8,
		.dst_transfer_width 	           = XMC_DMA_CH_TRANSFER_WIDTH_16,
		.src_transfer_width 	           = XMC_DMA_CH_TRANSFER_WIDTH_16,
		.dst_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		.src_address_count_mode = XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		.dst_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		.src_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		.enable_dst_linked_list    = true,
		.enable_src_linked_list    = true,
		.transfer_flow 			= XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
		.enable_src_gather		= true,
		.enable_dst_scatter		= false,
	};

	XMC_DMA_CH_CONFIG_t GPDMA0_Ch0_config =
	{
		{
		   .enable_interrupt 		= true,
		   .dst_transfer_width 		= XMC_DMA_CH_TRANSFER_WIDTH_16,
		   .src_transfer_width 		= XMC_DMA_CH_TRANSFER_WIDTH_16,
		   .dst_address_count_mode	= XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		   .src_address_count_mode 	= XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT,
		   .dst_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		   .src_burst_length 		= XMC_DMA_CH_BURST_LENGTH_8,
		   .enable_src_gather		= true,
		   .enable_dst_scatter 		= false,
		   .transfer_flow 			= XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA,
		},
	   .src_gather_interval		= 1,
	   .src_gather_count 		= 1,
	   .dst_scatter_interval 	        = 0,
	   .dst_scatter_count 		= 0,
	   .block_size 				= 8,
	   .transfer_type			= XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED,
	   .priority 				        = XMC_DMA_CH_PRIORITY_7,
	   .src_handshaking 		= XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE,
	   .src_peripheral_request 	= DMA0_PERIPHERAL_REQUEST_VADC_G0SR2_1,
	   .linked_list_pointer		= &liste1,
	};
	XMC_DMA_Init(XMC_DMA0);
	XMC_DMA_CH_Init(XMC_DMA0, 0, &GPDMA0_Ch0_config);
	XMC_DMA_CH_EnableEvent(XMC_DMA0, 0U, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
	NVIC_SetPriority(GPDMA0_0_IRQn, 9U);
	NVIC_EnableIRQ(GPDMA0_0_IRQn);
	XMC_DMA_CH_Enable(XMC_DMA0, 0);
}

Somehow i don´t get into my DMA interrupt handler and there is only one result in verify_ADC_Result1[0].
If i manually check verify_ADC_Result1[] and verify_ADC_Result2[] without the DMA by the ADC interrupt handler i get all results.
I just don´t get what is missing in my code.
The example did not help.
https://www.infineonforums.com/threads/3079-Linked-list-multi-block-DMA-transfer-with-DAVE-4-XMCLib
Please help without Apps.

Kind regards Gera Show Less

I have a problem to set up the external multiplexer for channel 6 of the group 1 of the adc.

here my code of the multiplexer part:


WR_REG( VADC->EMUXSEL, VADC_EMUXSEL_EMUXGRP1_Msk, VADC_EMUXSEL_EMUXGRP1_Pos, 1 );

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXSET_Msk, VADC_G_EMUXCTR_EMUXSET_Pos, 6 ); // external multiplexer channel max - 1 is selected
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXCH_Msk, VADC_G_EMUXCTR_EMUXCH_Pos, CVADC_MULTIPLEXER_CHANNEL ); // external multiplexer is connected to adc channel 6
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXCOD_Msk, VADC_G_EMUXCTR_EMXCOD_Pos, 0 ); // emux coding is normal
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMUXMODE_Msk, VADC_G_EMUXCTR_EMUXMODE_Pos, 3 ); // emux mode is sequence mode
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXST_Msk, VADC_G_EMUXCTR_EMXST_Pos, 1); // sample time control for emux conversions
WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXCSS_Msk, VADC_G_EMUXCTR_EMXCSS_Pos, 0 ); // emux channel select style, EMUXCH is channel number

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXWC_Msk, VADC_G_EMUXCTR_EMXWC_Pos, 1 ); // emux configuration write access enabled

VADC_G1->EMUXCTR = ulEmuxCtr;

WR_REG( ulEmuxCtr, VADC_G_EMUXCTR_EMXWC_Msk, VADC_G_EMUXCTR_EMXWC_Pos, 0 ); // emux configuration write access disabled

Thx in advance for your help Show Less