XMC™ Forum Discussions

I am a loyal user of Infineon.
I just came into contact with this one, there are fewer resources on the Internet, and who has XMC4000-related routines, can you share it?

For example, this REF-DAB11KIZSICSYS on the official website, the link is: https://www.infineon.com/cms/en/product/evaluation-boards/ref-dab11kizsicsys/ Show Less

I'm seeing a problem with the UART FIFOs on a XMC4700.
Perhaps there is an errata?

The "A" in UART stands for Asynchronous.
I'm trying to send 8 bytes , but I'm also receiving data at the same time. Most of the time, the transfers are all good.
But, occasionally, the transmit data is not what I expect. The transmit data appears to part of the data just received.

Initialization code:

   // Setup interrupts
    // Remote , BBB
    XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 1U);

    // Set service request for tx FIFO transmit interrupt
    XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 1);
 
    // Set priority and enable NVIC node for transmit interrupt SB USIC0_CH0 base = 84 + 1 (Nodepointer above)=85
    NVIC_SetPriority((IRQn_Type)85, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
    NVIC_EnableIRQ((IRQn_Type)85);

    // Turn off source of interrupts. They're turn on when FIFO is full
    UART_SB.channel->TBCTR  = UART_SB.channel->TBCTR & ~USIC_CH_TBCTR_STBIEN_Msk;

    // RX Interrupts
    // smallest frame is 6 bytes
    // Protocol is poor, the 2nd byte "length" is not accurate if any data is escaped
    // assume worst, go with 1 (0).
    // Can't switch trigger limits on the fly, need to go with 1

    XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 0U);
 
    // Set service request for Rx FIFO transmit interrupt
    XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 0);
    XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE, 0);
 
    // Set priority and enable NVIC node for receive interrupt SB USIC0_CH0 base = 84 + 0 (Nodepointer above)=85
    NVIC_SetPriority((IRQn_Type)84, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
    NVIC_EnableIRQ((IRQn_Type)84);

I've attached a scope capture of the problem.
The XMC4700 receives a CAN message (CAN 2F0 1 2E) on left. It converts this to a UART stream, should be "31 08 53 02 F0 2E xx 32". But as can be seen on "RS-232(RX) ... "31 08 53 00 00 00 70 32". The 4700 is transmitting this.
Just above is "RS232(Tx) ... 31 0A 53 03 81 00 00 00 70 32". The "70 32" is cut off a bit, but its there.
It appears that the transmit is read from the RX FIFO!
Is there some kind of race condition in the hardware?
And more important, is there a work around? Show Less

I am having difficulty downloading the ETHCAT_SSC_XMC43.zip from https://www.infineon.com/cms/en/product/promopages/aim-mc/dave_downloads.html. The site keeps returning a site cannot be reached error. How can I obtain this file so that I can complete the XMC4300 Relax EtherCAT App SSC Slave Example? Please Advise. Show Less

Hi I want to introduce to my code:
something like "enter_critical_section" and "exit_crtical_section".

This function shall disable all interrupt handling and sahll enable interrupt handling afterwards.
The must have is, that the interrupts that occured while disabled, shall be held pending and shall be handled after the call of "exit_critical_section".

I am not quite sure wheter __disable_irq and __enable_irq fullfill this requirement.

In xmc_math.c ther are the functions crtical_section_enter and crtical_section_exit. Do these functions do the job?
I am a bit confused because i expected to find a __enable_irq() in the function critical_section_exit ?

Maybe there is some kind of expert out there who can help me out on this, as the documentation is a bit confusing how to safely catch pending intterupts after re-enabling.

Best regards Sven



__attribute__((always_inline)) __STATIC_INLINE uint32_t critical_section_enter(void)
{
uint32_t status;
status = __get_PRIMASK();
__disable_irq ();
return status;
}

__attribute__((always_inline)) __STATIC_INLINE void critical_section_exit(uint32_t status)
{
__set_PRIMASK(status);
} Show Less

Hi,

I am trying to map 6 slaves to a single SPI master in DAVE. It gives me an error saying "DAVE is unable to grant your last hardware resources request".

I have referred to Universal Serial Interface Channel (USIC) AP3230332303 note and it clearly shows that 8 slave selects are available.

I do not want to daisy chain the slaves. Is there a certain way to configure 6 slave selects in DAVE?

Thanks in advance for the help.

Regards,
Abhijeet Show Less

What are other people doing with regards to find available devices?
I just looked to day, and > 52 week lead time!

In particular, XMC4700 series.
Are others switching to other brand of processors? Show Less