XMC™ Forum Discussions
I'm trying to use the DAP_MINIWIGGLER with a 10-pin connector. After I connected it to my laptop, I tried to measure the voltage between pin 3&5 using a DMM and it was 0V, then measured the voltage between pin 3&1 and it was also 0V ... according to my understanding it should be 5V ! Also I didn't notice any LED on after I connected the miniwiggler to the USB ! ... is this normal, or I have a malfunctioning DAP miniwiggler?
Also, I'd appreciate if I can get the schematic of the "KIT_DAP_MINIWIGGLER_USB"
Thanks,
Nour Show Less
I am working on a simple pulse generator using Dave App PWM_CCU8. The configuration of one of these slices is:
- Channel 1 direct output, passive state=After Compare Match, passive state=Low.
My question: How can the output forced to its passive level?
I found in this form the thread "https://www.infineonforums.com/threads/4670-XMC4500-how-to-force-CCU-slices-to-their-passive-levels", but for me, it is unfortuately not exactly enough. For example, when I set the PWM into multichannel mode (Channel 1 enable), the PWM generation doesn't start.
Can please someon provide a more complete example?
Regards, j. Show Less
Dear Krup,
we would like to know the relationship between the /CTRIP and /Enable in the FOC software.
/Enable TP301A.15 on XMC4400 board
/CTRIP0 TP301A.13 on XMC 4400 board
/CTRIP0 is monitored by ISR. and /Enable is controlled by state machine. Can we describe the /CTRIP0 detection sequence as following.
Power ON. ----> Software will check /CTRIP0
Branch 1, if /CTRIP0 = GND, Set /ENABLE to high.
Branch 2, if / CTRIP0 = High, Set /Enable to Low, ( enable the invertor).
Question:
1. Does XMC4400 provide a filter for CTRIP0 detection? and what is the sampling rate if level detection? What is the filter value?
2. Will XMC4400 enable the invertor before detecting the /CTRIP0?
Finally, where can we find the documentation for this question? or we have to read the code? If we have to read the code, may advice which function?
Regards
Hello!
I've been working on implementing PTP on the XMC4700, and I'm close to getting the timestamping setup working. However, I'm quite puzzled by the description of the TIMESTAMP_CONTROL.SNAPTYPSEL bitfield (XMC4700 reference manual page 1212). It simply says, "These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken." However, I can't find any other mention of this bitfield anywhere else in the datasheet, and there's no explanation anywhere of what the bits actually do. Could someone provide some clarification on how this bitfield affects the packets that are timestamped?
Thanks!
Show LessWe are using KIT_XMC4400_DC_V1 board, and using PMSM_FOC App from DAvE IED. We can read the I_V, user_speed_set. etc. However, the Inverter Enable could not be activated. ( Active_Low). We traced teh PMSM_FOC error code. It always show "2", Meaning " Trap". How to debug for such case? How can we know where give this "TRAP" ?
Show LessWe are implementing IEEE 1588 time sync on XMC4700 relax kit, we base on the DAVE example source code named "HTTP_SERVER_RTOS_XMC47". Our main function is as in the embedded code (print out timestamp of transmitted frame).
However, we always have same output, like "frame transmitted at 0 second, 4 nanosecond", this output only varies when I remove "malloc".
Inside the XMC_ETH_MAC_InitPTP function, I realized that the below assignment, the value of eth_mac->regs->TIMESTAMP_CONTROL always keeps 0, no mater what value I gave to the variable "config".
eth_mac->regs->TIMESTAMP_CONTROL = ETH_TIMESTAMP_CONTROL_TSENA_Msk | ETH_TIMESTAMP_CONTROL_TSCTRLSSR_Msk | config;
So my questions:
- Would any of you have solution?
- Is it possible/better to develop 1588 application without using library (like without using XMC_ETH_MAC_InitPTP from /HTTP_SERVER_RTOS_XMC47/Libraries/XMCLib/inc/xmc_eth_mac.h)? I mean we read/write register by ourself by refering the document "Reference Manual of XMC4700/XMC4800 Microcontroller" (the pdf with ~2893 pages)?
Thanks so much in advance for your help!
Thi
Show Less
////////////////////////////we define///////////////////////////
#define MAC_ADDR0 0x8C
#define MAC_ADDR1 0x04
#define MAC_ADDR2 0xBA
#define MAC_ADDR3 0x17
#define MAC_ADDR4 0x8A
#define MAC_ADDR5 0x4A
#define MAC_ADDR ((uint64_t)MAC_ADDR0 | \
((uint64_t)MAC_ADDR1 << 😎 | \
((uint64_t)MAC_ADDR2 << 16) | \
((uint64_t)MAC_ADDR3 << 24) | \
((uint64_t)MAC_ADDR4 << 32) | \
((uint64_t)MAC_ADDR5 << 40))
#define XMC_ETH_MAC_NUM_RX_BUF (4)
#define XMC_ETH_MAC_NUM_TX_BUF (4)
static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t rx_desc[XMC_ETH_MAC_NUM_RX_BUF] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) XMC_ETH_MAC_DMA_DESC_t tx_desc[XMC_ETH_MAC_NUM_TX_BUF] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) uint8_t rx_buf[XMC_ETH_MAC_NUM_RX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));
static __attribute__((aligned(4))) uint8_t tx_buf[XMC_ETH_MAC_NUM_TX_BUF][XMC_ETH_MAC_BUF_SIZE] __attribute__((section ("ETH_RAM")));
////////////////////////////we define///////////////////////////
int main(void)
{
DAVE_STATUS_t status;
status = DAVE_Init();
if(status != DAVE_STATUS_SUCCESS)
{
XMC_DEBUG("DAVE APPs initialization failed\n");
while(1U)
{
}
}
cgi_init();
ssi_init();
osThreadCreate (osThread(main_thread), NULL);
////////////////////////// our 1588 code ////////////////////////////
XMC_ETH_MAC_TIME_t *txTime;
char data[10];
uint32_t config = (uint32_t)ETH_TIMESTAMP_CONTROL_TSENALL_Msk;
memset(data, '\0', 10);
snprintf(data, 10, "%s", "mydata");
txTime = (XMC_ETH_MAC_TIME_t*)malloc(sizeof(XMC_ETH_MAC_TIME_t));
XMC_ETH_MAC_t ethMac =
{
.regs = ETH0,
.address = MAC_ADDR,
.rx_desc = rx_desc,
.tx_desc = tx_desc,
.rx_buf = &rx_buf[0][0],
.tx_buf = &tx_buf[0][0],
.num_rx_buf = XMC_ETH_MAC_NUM_RX_BUF,
.num_tx_buf = XMC_ETH_MAC_NUM_TX_BUF
};
XMC_ETH_MAC_InitPTP(ðMac, config);
lwip_send(0, data, sizeof(data), 1);
XMC_ETH_MAC_GetTxTimeStamp(ðMac, txTime);
printf("transmitted at %"PRIu32" second, %"PRIu32" nanosecond \n", txTime->seconds, txTime->nanoseconds);
////////////////////////// our 1588 code ////////////////////////////
osKernelStart();
}
Dear community members,
I have an issue regarding USB on XMC4500 and try to get any support.
In our application we are implementing 3 endpoints besides the default endpoint 0:
EP2 --> Bulk-IN
EP3 --> Bulk-OUT
EP4 --> Interrupt-IN
The XMC is configured as USB device in Buffer-DMA mode.
Currently we have an issue with the interrupt endpoint EP4. In our application we are transmitting 10 bytes data periodically (cycle time 5 seconds). The problem occurs when the 5th DATA packet is transmitted. The 5th DATA packet contains 5 bytes instead of 10 bytes. The first 4 bytes are correct, the last byte is wrong. Also there is a CRC error in this packet. We have detected these facts by using an USB tracer device, which was switched between the XMC and the USB host. The DMA buffer (DIEPDMA4 register) is configured correctly with the memory buffer which holds the data to transmit. Additionally the transfer size register (DIEPTSIZ4) is configured correctly, too:
DIEPTSIZ4.XferSize = 0xA
DIEPTSIZ4.PktCnt = 0x1
It is conspicuous that always the 5th packet causes this error (wrong packet length and CRC error) independent on the cycle time.
Furthermore we tested the behaviour with a packet length of 18 bytes instead of 10 bytes
DIEPTSIZ4.XferSize = 0x12
DIEPTSIZ4.PktCnt = 0x1
In this case just two packets were transmitted correctly. The 3rd packet contained 13 bytes instead of 18 bytes (again 5 byte less and again only the last byte was wrong).
Additionally we tried to send these packets via EP2 (Bulk-IN). This didn't cause any issues and all packets (more than 5 packets) were transmitted successfully.
Does anyone know, if there is any specific application requirement for Interrupt-IN endpoints which differs to Bulk-IN endpoints? Maybe there is any issue within the XMC4500 (I couldn't find any points in the current errata sheet V1.5).
Thanks!
Best regards,
autoUser
Show LessI am using xmc1300 development board for PFC stage in 3.4kW onboard EV charger. In the software for PI voltage control loop I have to set the max power limit as 3.4kw. This power limit is also used in duty cycle calculation for MOSFET gate signal. The max dc bus voltage at LLC stage is 64v and the max current rating is 53A. How to scale this 3.4kW power limit , so that I can use it in the software calculations. I am using DAVE 4.4.2 VERSION.
Show LessDear Colleagues,
We are currently trying to identify MCU for the upcoming eV charger project. Attach you can find pre-request which is defined by the customer. As you can see from attach file, they are requesting to have dual core because of the reasons I will explain in the below comments. We have focused on XMC4400 and Aurix TC36xx family & TC37x family, but analog futures of the Aurix (especially there are no comparators in the Aurix) lead us to go with XMC4400 family.
Asi mentioned, the XMC4400 seems to be the closest processor to the requirements of their project due to the analog peripherals it contains. While other processors in the XMC series or AURIX series may have higher clock speeds or parallel processing capabilities, it seems logical to focus on the XMC4400 due to the peripherals inside.
When we consider the blocks to be run in the software, the high frequency of software blocks such as adc result median filtering, adc result offset and gain conditioning, current and voltage control loop, coordinate transformations, grid phase locked loop, DC bus regulation, fast overvoltage protections, correlation grid cut detection) It must be run in the cut. The switching frequency we envisaged is 70kHZ, which gives us a maximum of 14.28usec to complete all processes. In addition, in the remaining time, functions such as various state diagrams and communications (CAN, I2C, Modbus Over UART) and various functions (Event Logging, Eeprom Memory Management, Low Speed Protections, Power Calculations) will be run on the background loop. In addition, we are considering using RTOS for task management. This will require an extra interrupt and extra processing load in the background loop.
The XMC44xx series has a maximum 120MHz single-core processing capability. Considering all these requirements, we thought of going over a structure with two cores and high processing capability, as we stated in the specification. Our main goal is to have backup processing cycles in order to realize the current requirements of the project and to add functions that are not currently foreseen at the end of the project, but that may be requested in the future. For this purpose, we will conduct a benchmark study among ourselves. I would be glad if you could help with this.
Show LessI'm interfacing an SPI-connected ADC chip to retrieve AD channel data from it.
Therefore I sent 2 transfers of 32 bit each to simultaenously receive 2x 32 bit. Each transfers starts with a chip select assertion and stops with chip select de-assertion.
Unfortunately the SPI speed cannot be increased above 5 MHz. TX/RX of whole 64 bits currently takes ~20 us. I'd rather use that time to perfom other operations than to wait for the data to become sent/received.
I though about using FIFO / DMA-driven transfer.
1. If using FIFO, can I prepare the FIFO once and send it again and again without the need to refill the TX FIFO? Is it possible to also add TCI (Transfer Control Information) then?
2. If using DMA-driven transfer, am I able to add TCI to the TX data so that chip select lines are correctly pulled?
Best regards,
Ernie T Show Less