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Solved! Go to Solution.
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Hi @User20456,
Upon further investigation, the following was found out:
The counting direction of the concatenated timer is fixed in the start and the timer can then either count up or count down but the direction cannot be updated on the fly. This can be found out on page 23-51 in XMC4700 XMC4800 Reference Manual
The counting scheme is done by the hardware and cannot be changed. The CCU4yCMC.TCE bitfield enables concatenation of slices and configuration for HW is done automatically internally with an edge-aligned mode timer.
So this means the timer slice containing the LSBs should always have the TCE bitfield set to 0 and the MSB slice will have the TCE bit field set to 1. Section 23.2.9 Timer Concatenation in XMC4700 XMC4800 Reference Manual describes about the CCU4yCMC.TCE bitfield.
In order to have both the up-counting and down counting operational, 2 CCU4 slices can be configured for up-counting and 2 other CCU4 slices can be configured to perform down-counting.
Thanks and regards,
Nikhil
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Hi @User20456,
The following thread may be useful for your project. Do take a look into it:
Regards,
Nikhil
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Hi,
In my opinion the timer concatenation does not work properly while the counter are counting downwards. Perhaps I'm doing something wrong. Which events should be connected to the concatenated counter (that is the higher 16 bits of my 32 bits counter)? I guess that the direction shouldn't be connected (CMC.UDS). Which event should be connected to CMC.CNTS in the higher 16 bit counter? The same that in the lower 16bits?
I found a solution that seems to work without concatenation. Status bit of lower counter connected to CMC.CNTS of higher counter. CMC.UDS of both counters connected to the same event (in my case a pin). Both counters are in edge aligned mode, compare mode, PR=PRS=CR=CRS=0xFFFF. What do you think about?
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Hi @User20456 ,
Find the project attached below.
The project implements a 32-bit counter capable of both up and down counting. PWM signal is generated from a CCU4 slice and is used as a trigger for the counting operation. 2 CCU4 slices are concatenated. The lower CCU4 slice receives the PWM signal. The direction of counting is controlled by setting the voltage level on COUNT_DIRECTION pin.
By default, up cunting is performed. If COUNT_DIRECTION is driven high, then down counting is implemented.
Best regards,
Nikhil
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Hi @User20456,
CCU4_Pulse is a CCU4 slice that generates a pulse train. This will be used to trigger the counting operation in the (CCU4_L + CCU4_H) counter. Pulse_out and Pulse_in need to be connected externally. Connect P3.10 (Pulse_out) to P1.10 (Pulse_in) externally.
Observe the UART log using any terminal emulator (eg:TeraTerm). The logs print the value of the TIMER register of the CCU4 slices. Here are the UART parameters:
- Baud rate: 115200 bps
- Data bits: 8 bits
- Stop bits: 1 bit
- Parity selection: No parity
Up-counting:
During up-counting (default operation), the logs appear as follows:
Down-counting:
For down-counting operation, uncomment the following code in main.c :
DIGITAL_IO_SetOutputHigh(&COUNT_DIRECTION);
The UART logs for down-counting appear as shown below:
Regards,
Nikhil
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Have you missed the external connection to be done while adopting to your board?
Do check it once.
Have the properties of the direction counting in CCU4 GUI been done properly?
Regards,
Nikhil
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Hi have run your example as is, directly on a Relax Kit board for XMC4700/4800. Here, intentionally I don't connect pulse in and pulse out, to be sure that the counters should not run. As you can see from the snapshots catched in a debug session, when the counters count downwards (DIGITAL_IO_SetOutputHigh(&COUNT_DIRECTION) uncommented), the high counter counts free-running. Am I missing something?
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Hi,
do you have any news?
Regards
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Hi @User20456,
Upon further investigation, the following was found out:
The counting direction of the concatenated timer is fixed in the start and the timer can then either count up or count down but the direction cannot be updated on the fly. This can be found out on page 23-51 in XMC4700 XMC4800 Reference Manual
The counting scheme is done by the hardware and cannot be changed. The CCU4yCMC.TCE bitfield enables concatenation of slices and configuration for HW is done automatically internally with an edge-aligned mode timer.
So this means the timer slice containing the LSBs should always have the TCE bitfield set to 0 and the MSB slice will have the TCE bit field set to 1. Section 23.2.9 Timer Concatenation in XMC4700 XMC4800 Reference Manual describes about the CCU4yCMC.TCE bitfield.
In order to have both the up-counting and down counting operational, 2 CCU4 slices can be configured for up-counting and 2 other CCU4 slices can be configured to perform down-counting.
Thanks and regards,
Nikhil