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User11773
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I'm seeing a problem with the UART FIFOs on a XMC4700.
Perhaps there is an errata?

The "A" in UART stands for Asynchronous.
I'm trying to send 8 bytes , but I'm also receiving data at the same time. Most of the time, the transfers are all good.
But, occasionally, the transmit data is not what I expect. The transmit data appears to part of the data just received.

Initialization code:
   // Setup interrupts
// Remote , BBB
XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 1U);

// Set service request for tx FIFO transmit interrupt
XMC_USIC_CH_TXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 1);

// Set priority and enable NVIC node for transmit interrupt SB USIC0_CH0 base = 84 + 1 (Nodepointer above)=85
NVIC_SetPriority((IRQn_Type)85, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
NVIC_EnableIRQ((IRQn_Type)85);

// Turn off source of interrupts. They're turn on when FIFO is full
UART_SB.channel->TBCTR = UART_SB.channel->TBCTR & ~USIC_CH_TBCTR_STBIEN_Msk;

// RX Interrupts
// smallest frame is 6 bytes
// Protocol is poor, the 2nd byte "length" is not accurate if any data is escaped
// assume worst, go with 1 (0).
// Can't switch trigger limits on the fly, need to go with 1

XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(UART_SB.channel, XMC_USIC_CH_FIFO_SIZE_16WORDS, 0U);

// Set service request for Rx FIFO transmit interrupt
XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, 0);
XMC_USIC_CH_RXFIFO_SetInterruptNodePointer(UART_SB.channel, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE, 0);

// Set priority and enable NVIC node for receive interrupt SB USIC0_CH0 base = 84 + 0 (Nodepointer above)=85
NVIC_SetPriority((IRQn_Type)84, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 63U, 0U));
NVIC_EnableIRQ((IRQn_Type)84);


I've attached a scope capture of the problem.
The XMC4700 receives a CAN message (CAN 2F0 1 2E) on left. It converts this to a UART stream, should be "31 08 53 02 F0 2E xx 32". But as can be seen on "RS-232(RX) ... "31 08 53 00 00 00 70 32". The 4700 is transmitting this.
Just above is "RS232(Tx) ... 31 0A 53 03 81 00 00 00 70 32". The "70 32" is cut off a bit, but its there.
It appears that the transmit is read from the RX FIFO!
Is there some kind of race condition in the hardware?
And more important, is there a work around?
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User11773
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Hi ErnieT,

UARTs setup by Dave Apps. Running at 416Kbaud. So running without FIFOs would be a problem. I'm quite sure its not a overlap problem.
The problem would appear when the read & write FIFO activity was about the same time.

View solution in original post

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User11773
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Update:
I added another UART and sent the same data to it. Original on Uart 0 Ch0, the new one on Uart 0 Ch 1.
When it fails, the new UART has the correct data.
So, pointing at a UART problem or perhaps I have a configuration issue.
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User11773
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There is still a UART problem.

I've managed to circumvent it by using another UART.
I do have a working system again, but I luckily only needed to add one jumper wire.
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User10696
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In your initialization code I cannot see where you set the size and starting position of the FIFOs. As the FIFO RAM is shared by 2 channels, it is very important to set the starting position of each FIFO correctly. I usually use 4 FIFOs each of 16 Bytes, starting at 0, 16, 32, and 48.
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Aashita_Raj
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Hi @TimFlynn,

Can you please attach your entire project here, so that we can check at our end?

Best Regards,
Aashita
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User11773
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Project attached.
Using Dave Apps.
This is the working version. UARTs configured as; UART_SB_RX, Direct, Receive FIFO enable & = 32. Tx FIFO disabled. USIC/0/ch/0
UART_SB_TX, Direct, Tx FIFO enable & = 32. Rx Fifo disabled. Usic/1/ch/0

This version works as required, but I had to modify boards for this configuration.
Prior version, that didn't work, had RX & TX on same USIC & channel with fifos = 16 for each Rx & Tx.
This prior version mostly worked, except when an Rx was occurring about the same time as a Tx.
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User11773
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Setup is in the Dave app. I also typically use 16 bytes per.
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User11773
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Any update?
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User11773
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Anyone? please
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User14604
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Hello Tim,

can you change the project to send manually (no FIFO)?

Also, are the FIFOs for different purposes correctly placed, so they don't overlap? Because of this:
This prior version mostly worked, except when an Rx was occurring about the same time as a Tx.

You need to set TBCTR.DPTR. If both RX and TX FIFOs start at position 0, they will overlap and you'll see strange behaviour.

Best regards,
ErnieT
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Aashita_Raj
Moderator
Moderator 100 solutions authored 250 replies posted 250 sign-ins
Moderator
Hi @TimFlynn,

Apologies for the late response. We went through your attached project. Since you mentioned about your prior version and the FIFOs size set to 16 for RX and TX, can you please let us know if your tried to use a single USIC channel block with the size of TX and RX FIFO set to 32 before this?
If yes, what were your possible observations ? Was it failing in that case as well ?

Also, can you please export the project and share? You can follow this ->File ->Export ->Infineon -> DAVE Project. I am mentioning this because I am facing difficulty in fetching some information
regarding the project.

Best Regards,
Aashita
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User11773
Level 4
First like received First solution authored
Level 4
Hi ErnieT,

UARTs setup by Dave Apps. Running at 416Kbaud. So running without FIFOs would be a problem. I'm quite sure its not a overlap problem.
The problem would appear when the read & write FIFO activity was about the same time.
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