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User12789
Level 3
Level 3
10 sign-ins First solution authored 5 sign-ins
I'm initializing the XMC4700 POSIF interface as described in the Reference Manual section that describes initialization. I've configured the module in Hall mode. When I write the initial expected/current Hall pattern into the POSIF0.HALPS register
and then write POSIF0.MCMS[STHR]=1 I expect to see the contents of POSIF0.HALPS to be copied to HALP, but this doesn't happen. The HALP register stays 0.

Is there some piece of configuration that I'm missing here that prevents the Hall Pattern Shadow Transfer from succeeding?

Note: I'm programming the registers directly rather than using XMCLib.
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1 Reply
Mike1
Employee
Employee
5 sign-ins First question asked 10 replies posted
Hi SodaAnt,

The POSIFx->MCMS.STHR bit should force the Hall Pattern shadow transfer. Please make sure that the POSIF is enabled. Here is a code snippet that shows how you could initialize the Hall and Output states:


uint8_t HallPat[16] = {010, 031, 062, 023, 054, 015, 046, 017, 010, 051, 032, 013, 064, 045, 026, 017}; // Current and Next Hall Pattern. First 8 are for one direction, second 8 are for the other direction. Note: Numbers are in Octal!
uint8_t halls, next_halls = 0;
uint8_t MotorDir = 0;

POSIF0->MCSM = 0x0000; // Turn Off All MOSFETs
POSIF0->MCMS = POSIF_MCMS_STMR_Msk;

// Set the current & Next Hall States & Shadow Regs
halls = (POSIF1->PDBG & POSIF_PDBG_HSP_Msk) >> POSIF_PDBG_HSP_Pos;
POSIF0->PRUNC = POSIF_PRUNC_CSM_Msk | POSIF_PRUNC_CRB_Msk; // Stop the POSIF and clear it's internal status

next_halls = HallPat[halls + MotorDir] >> 3;
POSIF0->HALPS = HallPat[halls + MotorDir];

POSIF0->MCMS = POSIF_MCMS_STHR_Msk; // Force shadow transfer of halls
POSIF0->HALPS = HallPat[next_halls + MotorDir];
POSIF0->PRUNS = POSIF_PRUNS_SRB_Msk; // Start POSIF

The above code snippet assumes that the POSIF is already enabled and initialized. The code snippet below shows one way that this could be done (note that your settings for PCONF will likely be different):
XMC_SCU_CLOCK_EnableClock(XMC_SCU_CLOCK_CCU);
XMC_SCU_CLOCK_UngatePeripheralClock(XMC_SCU_PERIPHERAL_CLOCK_POSIF0);
XMC_SCU_RESET_DeassertPeripheralReset(XMC_SCU_PERIPHERAL_RESET_POSIF0);


POSIF0->PRUNC = POSIF_PRUNC_CRB_Msk | // Clear the Run bit
POSIF_PRUNC_CSM_Msk; // Clear the internal state

POSIF0->MCMC = POSIF_MCMC_MNPC_Msk | // Clear the MultiChannel Update Enable MCMF.MSS
POSIF_MCMC_MPC_Msk; // Set Output to 0x0000

POSIF0->PCONF = ( (0 << POSIF_PCONF_FSEL_Pos) | // Hall Sensor Mode
(1 << POSIF_PCONF_HIDG_Pos) | // No Idle Mode
(1 << POSIF_PCONF_MCUE_Pos) | // MC Pattern Updated via SW
(0 << POSIF_PCONF_INSEL0_Pos) | // H0 (IN0A)
(0 << POSIF_PCONF_INSEL1_Pos) | // H1 (IN1A)
(0 << POSIF_PCONF_INSEL2_Pos) | // H2 (IN2A)
(0 << POSIF_PCONF_DSEL_Pos) | // HSDA for blanking delay
(0 << POSIF_PCONF_SPES_Pos) | // Rising Edge on blanking delay trigger
(3 << POSIF_PCONF_MSETS_Pos) | // MSETD to request MCM shadow transfer
(0 << POSIF_PCONF_MSES_Pos) | // Request MCM shadow transfer on rising edge
(0 << POSIF_PCONF_MSYNS_Pos) | // MCM Shadow Update Sync'd to MSYNCA
(0 << POSIF_PCONF_EWIE_Pos) | // Disable External Wrong Hall Event
(7 << POSIF_PCONF_LPC_Pos)); // Low Pass Filter set to 64 clocks

POSIF0->PFLGE = 0;

POSIF0->PFLGE = ( (1 << POSIF_PFLGE_ECHE_Pos) | // Enable Correct Hall Event (CHE) Interrupt
(0 << POSIF_PFLGE_EWHE_Pos) | // Disable Wrong Hall Event (WHE) Interrupt
(0 << POSIF_PFLGE_CHESEL_Pos) | // CHE uses node 0 (POSIFI0.SR0)
(0 << POSIF_PFLGE_WHESEL_Pos)); // WHE uses node 0 (POSIFI0.SR0)

POSIF0->PRUNS = POSIF_PRUNS_SRB_Msk; // Set module Run bit

Best regards,
Mike
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