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Not applicable
Hi there,

I am getting a hard fault for accessing an unaligned memory address with STR single word. Cortex M4 manual says that:

Unaligned support is only available for load/store singles (LDR, STR). Load/store double already supports word aligned accesses, but does not permit other unaligned accesses, and generates a fault if this is attempted.


What could be the possible reason of this fault?

My code is as follows. It throws an exception at STR.


PRESERVE8
THUMB
Stack EQU 0x00000100

AREA STACK,NOINIT,READWRITE,ALIGN=3
StackMem SPACE Stack

AREA RESET,DATA ,READONLY
EXPORT __Vectors
__Vectors
DCD StackMem + Stack
DCD Reset_Handler
ALIGN

AREA |.text|,CODE,READONLY, ALIGN=2

ENTRY
EXPORT Reset_Handler
Reset_Handler

MOV R5 , #0x3c92
MOVT R5 , #0x2000
MOV R4 , #0x123
STR R4 , [R5]

STOP
B STOP
END
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Not applicable
It seems that there was a built in issue with this processor so I manually configured CCR register which had an unalign trap bit. I simply cleared that bit and it worked. However, in documentation, the reset value of that bit was 0 but actually on reset it wasn't zero so I had to do a reset manually. Added following code in C source code:

#define CCR (*(volatile unsigned long *) 0xE000ED14)

CCR= 0x200; //Reset value of CCR register


and in assembly:

MOV R1, #0xED14
MOVT R1, #E000
MOV R2, #0x200
STR R2, [R1]
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