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User22479
Level 1
Level 1
Hallo All,

I was analyzing an issue with dominant state in CAN transceiver, during startup.
The issue was further narrowed down to the output of Micro controller xmc4500, which delays the reset pin (PORST) by 25 ms. PORST reset time as per data sheet is around 2 microseconds.

My question is, where can i find the time for Power validation. (Attachment).

Reference manual: xmc4500_series.pdf


Thank you in advance.

PS : i couldn't test on reference board, also the time taken to set PORST is causing the dely.

Regards,
Anuroop
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Alakananda_BG
Moderator
Moderator
Moderator
50 likes received 250 sign-ins 250 replies posted
Hi Anuroop,

I have attached the image below, can you let us know how this issue was narrowed down i.e. we want to know how you have confirmed the time take to PORST is causing the problem.
5336.attach

Regards
Alakananda
Alakananda
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User22479
Level 1
Level 1
Hallo Alakananda,

-> We have a CAN transciever that expects a Logic 1 from the ports of the uc to keep it recessive.
Unfortunatly, the uc port is not ready for 25ms or so, gives a logic 0, which makes the transciever in Dominant state.
(Ofcourse, this leads to a hw solution).
Also from the reference document.

Point 1) From XMC4500 reference document : Page :491
Power Validation
1. A power validation circuit monitors the internal core supply voltage of the core domain.
2. It monitors that the core voltage is above the voltage threshold VPV which guarantees
3. save operation. Whenever the voltage falls below the threshold level a power-on reset is generated.

Question >> Can you please check and let us know, the time to perform “Power Validation” in XMC_4500. (Attachement5359.attach)
is this 2us specified in data sheet is from RST_Gen or from VBAT (What is VBAT? :- Time, from which power is supplied to uC)

Point 2)

RST_Gen -> startup_XMC4500.S = 1.7ms
RST_Gen -> main.c = 5.4ms

I assume, PORST comes after RST_Gen.
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