XMC45 SPI, long time between bytes, even usign DMA.

[User2235]

Hi,
I'm trying to improve the throughput of the SPI of the "QSPI_EXAMPLE_XMC45".
Even using DMA for receive mode, there's a interval of the 1.56uS between bytes. It reduces the throughput for a maximum of (8/1.56) Mbps. I suppose it can not be that bad.
Someone knows how to reduce this interval to zero?

Ari.

[chismo]

Hello Ari,

The SPI delay times are influenced by the BRG register bit fields DCTQ, PCTQ and CTQSEL.

For minimal delay times, the settings should be:
- DCTQ and PCTQ = 0
- CTQSEL = 0x1

		/* clear DCTQ, PCTQ and CTQSEL bit fields */
		USIC0_CH0->BRG &= 0xFFFF003F; 
		/* set CTQSEL bit field to 0x1 */
		USIC0_CH0->BRG |= 0x40;

Can you try if the above helps?

Regards,
Min Wei

[User2235]

Chismo,

I found out that is necessary to setup the protocol handling of the SPI_MASTER[4.3.8] to use DMA to receive mode and to transmit mode also. Now the time between bytes is 100 nS.
I tested the settings you suggested, but it did not reduce this delay.

Is it possible to reduce this time to zero? Maybe combining DMA with FIFO?

Ari.

[User2235]

Another clue to this behavior:

Setting the SPI_MASTER[4.3.8] in Full Duplex and DMA, the bytes are transmitted without delay.

To transmit 256 bytes in QUAD-SPI takes 36.8 uS for 30MHZ clock and 31.4 uS for 60MHZ.
To transmit 256 bytes in Full Duplex takes 62.8 uS for 30MHZ clock and 34.2 uS for 60MHZ.

Ari.

[chismo]

Hello Ari,

To be sure, are you referring to the time between two frames, i.e. from SELO inactive to SELO active again?
Or are you referring to within the same frame, the interval between words, i.e. SELO is still unchanged during this time?

I assume is the former right? Because for the latter, there should not be any delay as long as the inter-word delay is not enabled through bit 24 (TIWEN) of PCR register.
To reduce the inter-frame timing, the PCR register bit fields DCTQ1, PCTQ1 and CTQSEL1 should be adjusted instead.
Sorry that I gave you the wrong register bit fields previously.

I tried with a XMC1000 kit that I have on-hand, generating a SCLK of 16 kHz.
At default settings, the inter-frame time is about 30.8 us.
With CTQSEL1 = 1, this duration falls into the nanosecond range.

Can you try again with PCR.CTQSEL1?
That said, I doubt it can be zero since I would imagine the hardware needing at least some peripheral clock cycles to handle the SELO signal.

Regards,
Min Wei

[User2235]

Min Wei,

For QUAD-SPI mode using DMA there's a delay of 100nS between bytes (words)
For Full-Duplex mode using DMA there's no delay between words.
I'm not using SELO.

Ari.