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Not applicable
Hello,
I set up a SPI connection on the XMC4300 using the USIC0_CH1 with the following pins :
CS (SELO0) : P2.3, SCLK (SCLKOUT) : P2.4, MISO (DX0A) : P2.2, MOSI (DOUT0) : P2.5.
For testing, I changed with success P2.3 with pin P1.14 (SELO2).

However, when I want to use another pins configuration, with USIC0_CH0, with the following pins:
CS (SELO0): P0.7, SCLK (SCLKOUT) : P0.8, MISO (DX0D) : P5.0, MOSI (DOUT0) : P1.5,
It doesn’t work.
Any ideas why ?

The register configuration are the same, except for the pins and for the input control register (DXOCR.DSEL)

Here my configuration :


/* Release reset of USIC module by writing a 1 to the USICxRS bit in SCU_PRCLR0 or SCU_PRCLR1 registers */
SCU_RESET->PRCLR0 |= (1<<11);

// ------------------------------------------------------------
// 1.Enable USICx channel n
// ------------------------------------------------------------
// Mode Control RM 18.2.2.2, Kernel State Configuration Register RM 18.11.3.3 :
// BPMODEN MODEN
SPI_CH->KSCFG |= (1 << 1)| (1 << 0);
// Run mode 0 : Channel operation as specified, no impact on data transfer

// Channel Control Register RM 18.11.3.1
// Select SSC Mode for USIC Channel 0 : put at 0 for configuration
//SPI_CH->CCR &= (0 << 3)| (0 << 2)| (0 << 1)| (0 << 0);
// ------------------------------------------------------------


// ------------------------------------------------------------
// 2.Configure Baud Rate Generator Register (BRG) RM 18.11.6.2
// - Normal divider mode
// - Baud rate = SCLK
// - PDIV (Divider factor) = 71 -> SCLK = 1 Mbit/s / PDIV = 5 -> SCLK = 12 Mbit/s / PDIV = 8 -> SCLK = 8 Mbit/s
// - Delay : Tld = 10 us with CTQSEL = 2 and DCTQ = 10 for SCLK = 1 Mbit/s
// - Delay : Tld = 10.3 us with CTQSEL = 2, DCTQ = 31 and PCTQ = 3 for SCLK = 12 Mbit/s
// - Delay : Tld = 1 us with CTQSEL = 2, DCTQ = 1 and PCTQ = 7 for SCLK = 8 Mbit/s
// - Delay : Tld = 6 us with CTQSEL = 2, DCTQ = 6 and PCTQ = 7 for SCLK = 8 Mbit/s
// - Delay : Tld = 8 us with CTQSEL = 2, DCTQ = 8 and PCTQ = 7 for SCLK = 8 Mbit/s
// - SCLKCFG = 00b, cf RM 18.4.1.2 Shift Clock Signals : data transmitted on the rising edge of the clock and the data received on the falling edge of the clock (CPOL = 0, CPHA = 0)
// - SCLKOSEL = 0b : SCLK from the baud rate generator is selected as the SCLKOUT input source.
// - CLKSEL = 00b : the fractional divider frequency Ffd is selected
// - PPPEN = 0b : This bit defines the input frequency fPPP. PPPEN = 0b : The 2:1 divider for fPPP is disabled, fPPP = fPIN = 144 mhz .
// ------------------------------------------------------------
// DM = 0b01 STEP = 1023 = 0x3FF = 0b001111111111
SPI_CH->FDR = (1 << 14) | ( 1023 << 0);
// PDIV DCTQ CTQSEL PCTQ SCLKCFG
SPI_CH->BRG = (8 << 16) | (1 << 10) | (2 << 6) | (3<<8) ; //| (2 << 30)
// ------------------------------------------------------------


// ------------------------------------------------------------
// 3.Configure input stages : Input Control Registers RM 17.11.5.1
// - Select input DX0A -> DSEL = 0b000, input DX0D -> DSEL = 0b011
// - Derive input of data shift unit directly from input pin
// - DSEN = 1 : The synchronized signal can be taken as input for the data shift unit.
// cf RM 18.11.5.1 Input Control Registers and RM 18.4.3 Operating the SSC in Master Mode
// - INSW = 1 : The input of the data shift unit is connected to the selected data input line. This setting is used
// if the signals are directly derived from an input pin without treatment by the protocol preprocessor
// ------------------------------------------------------------
// DSEN INSW DSEL
SPI_CH->DX0CR = (1 << 6) | (1 << 4) | (0b011 << 0);
// ------------------------------------------------------------


// ------------------------------------------------------------
// 4.Configure data format : SCTR Shift Control Register RM 18.11.7.1
// - Data word = 16 bits
// - FLE = 63 : the lengh of the frame is not set, and external fctors can end the transmision, not based on frame length
// - PDL = 0 : This bit defines the output level at the shift data output signal when no data is available for transmission. passive level is 0
// - SDIR = 1 : MSB first
// - TRM = 01b :The shift control signal is considered active if it is at 1-level. This is the setting to be
// programmed to allow data transfers.
// - DSM = 00b : Data Shift Mode : Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0
// ------------------------------------------------------------
// WLE = 0xF FLE (63 = infinite) TRM SDIR
SPI_CH->SCTR = ( 15<<24 ) | ( 63<<16 ) | ( 1<<8 ) | ( 1<<0 );
// ------------------------------------------------------------


// ------------------------------------------------------------
// 5.Configure data transfer parameters : TCSR Transmission Control and Status Register RM 18.11.7.2
// - Single shot transmission of data word when a valid word is available
// - WLEMD = 0b : WLE Mode means the TCSR.EOF (End Of Frame) bit is not automatically changed.
// - SELMD = 0b : we have only one slave: Select Mode : automatically update bit field PCR.CTR[20:16] by the transmit control information TCI[4:0] and clear bit field
// - PCR.CTR[23:21] (see Page 18-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the
// transmit buffer input locations TBUFx or by an optional data buffer.
// - WLE Mode : This bit enables the data handler to automatically update the bit field SCTR.WLE by the transmit control information TCI[3:0] and bit TCSR.EOF by TCI[4]
// (see Page 18-33). If enabled, an automatic update takes place when new data is loaded to register TBUF, either by writing to one of the transmit buffer
// input locations TBUFx or by an optional data buffer.
// - SOF = 1b : Start of Frame : The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated
// (respecting the programmed delays).
// So after have sending a frame, the PCR.MSLSEN (slave select) is automatically deactivated.
// So the Slave Select is deactivated after send 8 bits.
// - EOF : End of Frame : If it is the last word, the MSLS signal becomes inactive after the transfer, respecting the programmed delays. This bit becomes
// cleared when the TBUF data word is transferred to the transmit shift register.
// - EOF = 1b : The data word in TBUF is considered as last word of an SSC frame.
// - TDSSM = 1b : TBUF Data Single Shot Mode: data in TBUf is considered inactive after being moved into the shift register, send data only once.
// - TDEN = 01b: TBUF Data Enable : A transmission of the data word in TBUF can be started if bit TDV = 1.
// ------------------------------------------------------------
// TDEN TDSSM
SPI_CH->TCSR = (1 << 10) |(1 << 8);
// ------------------------------------------------------------


// ------------------------------------------------------------
// 6.Configure SSC protocol-specific parameters : SSC PCR Protocol Control Register RM 18.4.5.1
// - Slave select generation is enabled : MSLSEN = 1
// - Direct slave select mode is selected
// - End of frame condition is required for the frame to be
// considered as finished
// - SELO0 is selected as the active select signal with (1<<16)
// - SELO2 with (1<<18)
// - CTQSEL1 = 0b10 = 2 -> fCTQIN = fsclk
// - PCTQ1 = 0 and DCTQ1 = 9 -> delay 10 us for fsclk = 1 Mbit/sec
// - PCTQ1 = 1 and DCTQ1 = 23 -> delay 6 us for fsclk = 8 Mbit/sec
// ------------------------------------------------------------
// TIWEN SELO SELCTR MSLSEN CTQSEL1 DCTQ1 PCTQ1
SPI_CH->PCR = (1 << 24 ) | (1<<16) | (1<<1) | (1<<0) | (2<<4) | (23<<8) | (1<<6);
// ------------------------------------------------------------


// ------------------------------------------------------------
// 7.Enable SSC protocol
// ------------------------------------------------------------
// MODE
SPI_CH->CCR = (1 << 0);



//================================================
// U0C0
// INPUT - MISO - P5.0 - USIC0_CH0.DX0D -> P5_IOCR0 -> PC0 -> bits [7-3]
// DX0D : change Input control register
//PORT5->IOCR0 |= 0b00000000000000000000000000000000; // direct input, no internal pull device active

// OUTPUT - MOSI - P1.5 - USIC0_CH0.DOUT0 -> P1_IOCR4 -> PC5 ( because P1.5) -> bits [15-11]
// U0C0.DOUT0
// Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT1->IOCR4 |= 0b00000000000000001001000000000000;


//CLK - P0.8 -> P0_IOCR8 -> PC8 -> bits [7-3]
// USIC0_CH0.SCLKOUT
//Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT0->IOCR8 |= 0b00000000000000000000000010010000;

// Slave Select SELO0 - P0.7
// P0.7 -> P0_IOCR4 -> PC7 -> bits [31-27]
// SELO0 -> Check PCR register
// Alternate function 2 (cf RM p 2496 26.10.1 Port I/O Function Table ) -> 10010b
PORT0->IOCR4 |= 0b10010000000000000000000000000000;



Thank you in advance,
Nicolas
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2 Replies
jferreira
Employee
Employee
First like received 750 replies posted 500 replies posted
Hi,

Pins P0.7 and P0.8 are hardware controlled after reset (JTAG Pins).
You will need to reset the HWSEL register.

PORT0->HWSEL = 0;


Regards,
Jesus
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Not applicable
Thank you !!!
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